SAN RAMON, CA, UNITED STATES, February 19, 2025 — YorChip, Inc. in collaboration with its design partner SiliconIPs announces development of a 50nS latency 100G Ultra Ethernet ready Mac/PCS IP core. The IP is optimized for size, power and latency and targets edge AI applications as well as Data Center Accelerator
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CAMPBELL, Calif., February 18, 2025 – Arteris, Inc. (Nasdaq: AIP), a leading provider of system IP which accelerates system-on-chip (SoC) creation, today introduced FlexGen, a revolutionary, smart network-on-chip (NoC) interconnect IP. FlexGen from Arteris dramatically accelerates chip development while optimizing performance efficiency, addressing the rising demand for faster, more sustainable innovation
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Cwmbran, United Kingdom– 11/02/2025 – Thalia Design Automation is thrilled to announce the immediate availability of the latest version of the AMALIA Suite, their AI-powered industry end-to-end IP reuse platform.
This release brings significant enhancements throughout AMALIA, particularly within its Layout Automation Suite. The solution retains the intrinsic value
ATLANTA, GA, February 10, 2025 – Silicon Creations, a leading provider of high-performance analog and mixed-signal intellectual property (IP), today announced the successful tape-out of a chip on the TSMC N2P process including a novel temperature sensor design and an expanded portfolio of clocking IP to support next-generation semiconductor products.
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Mannheim, Germany, January 30, 2025 — EXTOLL, a leading provider of high-speed and ultra-low-power SerDes and Chiplet connectivity, has been selected by BeammWave, an innovation leader in mmWave 5G/6G digital beamforming, as a key SerDes IP supplier for its next gen communication ASIC development portfolio on GlobalFoundries’ (GF) 22nm FD-SOI process
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Munich, Germany, and Oxford, UK – 28th January, 2025 — Codasip GmbH and RED Semiconductor International Ltd have signed a Memorandum of Understanding (MoU) to collaborate on developing advanced AI acceleration technologies.
Under the MoU, RED will leverage the Codasip Studio processor design tools to integrate its VISC technology as an accelerator for Codasip