The corner-based timing signoff approach is a historical and traditional method that has justified a development and enhancements of conventional STA tools and signoff flows. The number of signoff corners exponentially grows along with an increase of variation sources, their magnitude, and timing margins. It becomes a bottleneck in the design flow and leads to a risk of silicon fail-ure, an over-margining, over-design, a loss in the System-On-Chip (SoC) performance, timing yield, cost, etc. It causes a timing signoff deadlock and still does not guarantee against a silicon failure. This paper examines the situation and outlines possible solutions.
Chapter 2 discusses the corner-based timing signoff methodology and the corner number used in this methodology. It explains why the corner number grows exponentially and is becoming a challenge. It increases the duration of the timing signoff, makes timing closure difficult and worsens most of design metrics. The corner-based timing signoff is a justification for the current design flow and contemporary STA/SSTA signoff tools. It has multiple impacts on the design flow, Time-to-Market (TTM), cost, SoC performance F, timing yield Y, etc. It becomes a prob-lem for getting the most benefits from moving to next advanced technology nodes.
Chapter 3 discusses the conventional timing signoff methodology in details. It starts with a defi-nition of the current timing closure and the timing yield. It shows that the conventional timing signoff does not support the timing yield as a design signoff requirement and it becomes a chal-lenge. Then, timing derating (margins) methods of contemporary STA tools, which should cover for variations, are considered. An increase of variation sources and their magnitude leads to loss-es in the SoC performance and diminishes other design metrics. Some limitations and drawbacks of current derating methods are considered and, then, it is shown that Statistical STA (SSTA) tools provide a partial solution but are not panacea. Later, in this chapter, we consider a signoff optimism and conservatism (pessimism), different variability sources and, finally, the timing signoff deadlock.
Chapter 4 outlines new advanced timing signoff paradigms and methods that have been mainly developed at Abelite Corp. (POCV is Synopsys’ upcoming method). Namely, it discusses the following 4 options that may be adopted by the EDA industry: Option 1—Enhancing the AOCV derating method; Option 2— Switching to the Parametric OCV (POSV); Option 3— Developing pseudo-statistical tools; Option 4— Developing statistical Monte Carlo-based tools. Options (1) and (2) may be combined with minimizing the corner number and using a detailed examination of variations in found risky (timing critical) paths. Options (1), (2) and partially (3) may be con-sidered if a company is using the corner-based signoff and this is a must-to-use method for the company no matter what it takes. Options (3) and (4) may be more beneficial as it is shown in the chapter. Finally, Options (3) and (4) are computationally expensive, especially Option 4 and there is a challenge with their validation. It is not likely they will replace the AOCV/POCV in the best-in-class PrimeTime [1] and ICC [2] tools, but they can be used on top of PrimeTime (after a PT run).
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This is a guest post by Dr. Alexander Tetelbaum, CEO of Abelite Design Automation
