Published Date: May 20, 2026
Advanced Micro Devices, Inc, 2485 Augustine Drive, Santa Clara, CA 95054
Job Description:
At AMD, we are dedicated to building innovative products that enhance next-generation computing experiences across various domains, including AI, data centers, PCs, gaming, and embedded systems. Our culture emphasizes collaboration, bold ideas, and a commitment to excellence, making us a leader in addressing the world's most pressing challenges. Join us to shape the future of AI and advance your career in a dynamic environment.
Responsibilities:
- Contribute to ASIC design for high-performance network chips, specifically AINIC and DPU.
- Engage in Ethernet subsystem design and integration.
- Design and implement switch fabric, buffer, and queue systems.
- Perform front-end RTL design and integration of high-speed I/O subsystems.
- Collaborate with architecture, IP, and physical design teams to ensure first-pass silicon success.
- Support post-silicon bring-up and yield learning.
Qualifications:
- Bachelor's or Master's degree in Computer Engineering or Electrical Engineering.
Skills:
- Knowledge of Ethernet protocols, switch design, and buffer/queue management.
- Understanding of high-speed I/O (SerDes) architecture, design, and verification.
- Experience with VCS simulation tools, Perl/Python/Shell scripting, and SystemVerilog/Verilog RTL design.
