SR ASIC Design Engineer – NoC & AXI Interconnect

At AMD, we are dedicated to creating innovative products that enhance next-generation computing experiences across various domains, including AI, data centers, PCs, gaming, and embedded systems. Our culture emphasizes collaboration, bold ideas, and a commitment to excellence, making us a leader in addressing the world's most pressing challenges. Join us to shape the future of technology and advance your career in a dynamic environment.

Responsibilities:

• Contribute to ASIC design for high-performance network chips: AINIC and DPU.
• Work within the NTSG ASIC Design Team to develop cutting-edge designs.
• Collaborate with architecture, IP design, physical design teams, and product engineers to ensure first-pass silicon success.
• Engage in Network-on-Chip (NoC) design and integration.
• Design and verify AXI, ACE, and APB interfaces.
• Implement queuing systems and manage buffer design.
• Provide post-silicon bring-up support and yield learning.

Qualifications:

• Bachelor's or Master's degree in Computer Engineering or Electrical Engineering.
• Understanding of Network-on-Chip (NoC) architecture and protocols.
• Experience with AXI, ACE, and APB interface design and verification.
• Knowledge of queuing system design and buffer management.

Skills:

• Proficiency in VCS simulation tools.
• Experience with Perl, Python, or Shell scripting.
• Familiarity with SystemVerilog/Verilog RTL design.
• Strong communication and problem-solving skills.
• Detail-oriented and highly accurate.