By Ramtera Design Automation | Technical / industry article for AnySilicon
For semiconductor design teams, the challenge is not simply completing a layout. It is getting there with predictable verification results, manageable tool costs and support when a project approaches tapeout. Ramtera Design Automation is addressing those needs with two complementary electronic design automation (EDA) engines: LVR for physical verification and PRE for place-and-route.
The immediate headline is a measurable physical verification result. In a published comparison across 42 reference designs on GlobalFoundries 22FDX, 12LP and 12LP+, Ramtera reports that LVR reproduced Siemens Calibre design rule checking (DRC) violation markers exactly: the same rule, location and count, with no missed or additional markers in this test set. That gives prospective users a concrete starting point for evaluating LVR as a pre-signoff verification engine.
Design teams typically run DRC repeatedly while fixing layout errors. Those iterative checks can consume access to expensive signoff verification resources. A pre-signoff engine that agrees closely with the reference flow can help teams debug earlier, reserve qualified signoff resources for final approval and potentially reduce verification licensing pressure.
Ramtera’s published comparison uses the same layout data and reference DRC results for each design. LVR executes the foundry rule deck and its output is compared marker by marker with Calibre—not just by rule count. Across the 42 cited designs, Ramtera reports 100% recall and 100% precision for the compared violation markers. These are Ramtera-reported results on a defined validation set, not a claim of universal equivalence across every possible design or rule deck.
LVR is explicitly positioned as a complement to, not a substitute for, foundry-qualified final signoff. This distinction allows teams to assess practical cost and cycle-time savings without changing their final signoff obligations.
LVR provides design rule checking, layout-versus-schematic (LVS), electrical rule checking (ERC), XOR comparison and related physical verification functionality. Its workflow supports multithreaded execution, scripted runs and standard results-database integration. Ramtera also reports a successful LVS run on a GlobalFoundries 22FDX reference design. Validation should be performed on each prospective customer’s target PDK, decks and layouts.
For evaluation, Ramtera proposes delivering LVR as a container that runs inside a customer’s own network. This allows an engineering team to test an already signed-off block while retaining its sensitive GDS data and rule decks in its existing infrastructure. Ramtera can assist with installation, rule-flow setup, result comparison, debugging and adoption into the customer’s verification cycle.
The complementary product, PRE, is a place-and-route engine covering floorplanning, placement, legalization, clock-tree synthesis, timing optimization, global routing and detailed routing. In Ramtera’s published open-PDK demonstration, the same PRE flow routed a 32-bit RISC-V core across SkyWater sky130, GlobalFoundries GF180MCU and IHP SG13G2.
Connectivity was checked independently with KLayout. Across the nine reported routed layouts, the verification found zero opens and zero unreached pins. On sky130, a small GCD block completed routing with zero DRC violations and zero opens. Timing closure and remaining DRC work on larger cores are still being improved, so the result should be read as evidence of functioning implementation and connectivity—not a claim that all tested cores are tapeout-ready.
Placement is a notable part of the published PRE benchmark story. Ramtera reports 24%–51% lower half-perimeter wire length than OpenROAD on its benchmark set. In a separate GCD experiment, feeding PRE placement into OpenROAD’s detailed router produced 27.6% less routed wire length and 40.8% fewer vias. The comparisons are design-specific, but they offer an objective basis for customer-led evaluation.
The commercial proposition is straightforward: customers may adopt LVR independently for pre-signoff verification or combine PRE and LVR for a connected digital implementation and verification workflow. PRE converts a synthesized netlist into a routed physical design; LVR checks the resulting layout and provides actionable verification feedback. Iteration between routing and verification can help teams converge toward a cleaner design before the final qualified signoff run.
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NETLIST |
PRE |
ROUTED LAYOUT |
LVR |
FINAL SIGNOFF |
Illustrative workflow: PRE and LVR support implementation and pre-signoff preparation; final signoff remains with the foundry-qualified flow.
Ramtera is offering special early-adopter commercial terms, including substantial introductory discounts on LVR and bundle pricing when PRE is included. Actual savings depend on customer requirements, license configuration and evaluation scope; no universal savings percentage is asserted. Ramtera also offers direct engineering assistance for setup, benchmark correlation, workflow integration, ramp-up and tapeout preparation.
The fastest path to a buying decision is a controlled proof of value. For LVR, Ramtera invites teams using GF22FDX, GF12LP or GF12LP+ to run a previously signed-off block and compare reference DRC results. For PRE, teams working with supported open PDKs can evaluate their own netlist and timing constraints, then inspect routed DEF, connectivity, timing and physical metrics. GlobalFoundries 22FDX customers can discuss PRE early access and specific flow requirements.
Rather than asking a customer to replace its entire flow at once, Ramtera proposes measurable acceptance criteria: DRC marker agreement, successful routing connectivity, runtimes, resource use, design-rule closure, and effort to integrate with existing tools. A clear evaluation makes the performance and commercial case testable.
Ramtera is also developing LVR-PEX for parasitic extraction. On a small Nangate45 GCD test, its LEF/DEF extraction matched OpenROAD OpenRCX on per-net ground, coupling and total capacitance for all 483 routed signal nets, as well as aggregate per-net resistance and driver-to-load resistance on 886 paths. Detailed SPEF record topology and Elmore-delay matching remain in development, and GDS-based extraction has only early smoke-test evidence. LVR-PEX is therefore an emerging extension of the portfolio, not a presently established replacement for a production-qualified extraction flow.
Ramtera is seeking evaluation partners among fabless companies, ASIC developers and semiconductor engineering service providers. Customers can request an LVR demonstration, benchmark correlation on an existing block, a PRE implementation trial or commercial terms for the combined bundle. Early adopters can discuss discounted licensing and direct engineering support tailored to their ramp-up needs.
To discuss an evaluation or early-adopter offer: sameer@ramtera.com | www.ramtera.com
About Ramtera:
Ramtera Inc. is a US-incorporated EDA company with research and development in Bengaluru, India. Its products include LVR for physical verification and PRE for place-and-route.
Source references: ramtera.com/ramtera-lvr-calibre-match.html ; ramtera.com/ramtera-pre-open-pdk-riscv.html. Product performance statements in this article are based on Ramtera-published measurements. Calibre is a trademark of Siemens; the foundry and open-source project names belong to their respective owners. Ramtera is not affiliated with or endorsed by Siemens or GlobalFoundries.