Semiconductor Latest News

What’s wrong with RTL for ASIC designs?

I think this is an appropriate first post, because this is a question that we’ve heard many times when talking with hardware engineers trying to sell our product. The fact that there are (now) about a dozen companies trying to replace RTL with alternatives (I’ll talk about HLS in other

ASIC Price Calculator

The ultimate ASIC calculator is available live on AnySilicon’s  website. Together with our Die Per Wafer calculator this ASIC price calculator provides a very accurate final price for ASICs. Please note, we did not include shipping cost therefore you may want to add this to the total prices.
As always,

Die Per Wafer Calculator

Die Per Wafer (DPW) online calculator is free and available live on AnySilicon website. The die per wafer calculator is simple to use and very accurate, however the results are estimates.
 
 
Now when you have the number of dies per wafer, you may want to consider:
 
See

If Your Chip Is Not an SoC, It Soon Will Be

Last week’s post was addressed primarily to those of you who are already designing SoCs. We made the point that more and more SoCs have multiple processors, either homogenous or heterogeneous, and that most or all of those processors do or will have caches. This led to the main conclusions of the

Moore’s Law Will Not Come To An End Anytime Soon

Gordon Moore said‚ on the 40th anniversary of his law that “Moore’s law is really about economics.” What did he really mean by that? In 1965 when Gordon Moore put forth Moore’s law based on his observation, those years were Golden years of Free Market Capitalism in America. The entire decade

Setup/hold interdependence in the pulsed latch (Spinner cell)

This is a guest post by Dolphin Integration which provides IP core, EDA tool and ASIC/SoC design service.
                                                                       

The IP Blame Game

This is a guest post by Methodics that delivers state-of-the-art semiconductor data management (DM)  for analog, digital and SoC  design  teams.

The topic of IP quality in the SoC era is difficult to define, and solutions to problems relating to IP quality, verification, and use are hard to find. Debates rage between IP users, suppliers,

TSV Integration is Creating Growth

“The long term growth of the equipment & materials business will be supported by the expansion of 3D TSV stack platforms” says Yole (Yole Développement) in its latest report, “Equipment & Materials for 3DIC & WLP Applications“. The market research and strategy consulting company, Yole proposes a deep analysis of the equipment &

The Macroeconimics of 450mm Wafers

SEMICON West 2014 in San Francisco was a great place to meet bloggers in the semiconductor industry to get updated on the status of 450mm diameter silicon wafers. On one side, there is a good news about the unprecedented level of collaboration taking place between the design and construction professionals

Efficient Verification and Virtual Prototyping of Analog and Mixed-Signal IP and SOCs Using Behavioral Models

This paper describes the use of behavioral models and mixed-signal simulation as a means to verify the proper instantiation, connectivity and control of analog and mixed-signal (AMS) intellectual property (IP), and also as a means to prototype an AMS integrated circuit (IC) or system-on-chip (SOC) using behavioral models in place