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This is a guest post by Naman Gupta, a Static Timing Analysis (STA) engineer at a leading semiconductor company in India.
In accordance with the Moore’s Law, the number of transistors on integrated circuits doubles after every two years. While such high packing densities allow more functionality to be incorporated on
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It’s no secret that Google, Amazon and Apple are heavily involved in the semiconductor industry. Apple itself is the biggest buyer of chips and estimated to buy 10% of chips sold worldwide. Google uses Intel’s CPUs in their server farms and represent alone 4% of Intel total sales.
Both
Chip production testing is probably the most underestimated task by ASIC development engineers. And yet, testing is an essential step with a direct impact on final chip cost.
Let’s start with the basics. Testing of chips is necessary because the chip manufacturing process cannot provide 100% yield. Silicon foundries
While assembly houses are gradually becoming more and more organized in regards to following internal processes, it seems that we, their customers, are often trying to push them to make shortcuts only because “we are running out of time”.
With chip design cycle time shrinking, production related tasks such
This is a guest post by Naman Gupta, a Static Timing Analysis (STA) engineer at a leading semiconductor company in India.
Electrostatic Discharge and Electromigration might sound similar, but refer to two different physical phenomena. Let’s take them up one by one.
Electrostatic Discharge (ESD) is the large current flow between any
Each year, top foundries are ranked by their sales, and you probably don’t need the table below to know who’s first.
But what if we look at the top foundries from the capacity angle? Each of the top foundries holds several production lines that address different technology nodes and wafer
This is a guest post by Naman Gupta, a Static Timing Analysis (STA) engineer at a leading semiconductor company in India.
Lock-Up Latches are important elements for STA engineer while closing timing on their DFT Modes: particularly the hold timing closure of the Shift Mode. While shifting, the scan chains
Maskset cost is becoming one of the major expenses to the overall NRE cost of ASIC projects, particularly with advanced technology nodes. For projects targeting low volume production the maskset cost is a financial barrier to a profitable and solid business.
Taping out using MLM instead of a full maskset
Dr. Morris Chang is not my hero. He might be the most important person in the semiconductor industry in our lifetime, but he is not my hero. I have nothing against him. I’ve never met him and probably will never will. Instead, I meet my heroes usually after tape-out,
Simply defined, Latch-Up in VLSI is a functional chip failure associated with excessive current going through the chip, caused by weak circuit design. In some cases Latch-Up can be a temporary condition that can be resolved by power cycle, but unfortunately it can also cause a fatal chip failure.
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