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QFN Package Overview

QFN package is probably the most successful package type today. Offering low price, excellent performance and small size, it is an ideal package for many applications.

 
QFN (quad-flat no-leads) is a plastic SMT package consisting of: a leadframe, single or multiple dies, wirebonds and a molding compound. The

Packaging and Delivery Methodology for: wafer, die and ICs

There are many ways to deliver, package and transport silicon products. Here’s a short primer that provides the basic facts regarding how silicon can be packed and delivered to ensure safe transportation with minimum damages.
 
There are two main options for receiving wafers from your foundry: tested or untested.
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Top 10 Semiconductor Companies Leaders Growth and Winners

This post describes the growth of top 10 semiconductors companies in the last 10 years. It tracks the growth of the 10 semiconductor leaders from 2002 to 2011 and shares some nontraditional thoughts about the ten semiconductors vendors’ success:
 
Thought #1: Follow the market trends
Since the 80’s companies from USA,

Who is Intel’s biggest Threat?

Paul Otellini has made the best decision for himself and for Intel. He is leaving the company.
There are only a few who don’t admire Intel. Intel has introduced ground breaking technologies decade after decade and has been demonstrating top financial results year after year. Is it beneficial for Intel

Copper (Cu) Wire Bonding Technical Benefits Overview

We love copper (Cu) wire. In fact, we already described in our post “Copper Wire (Cu) Reduces Package Cost” the cost advantages of copper wire bonding compared to Gold (Au) wire. Copper wire introduced some challenges to assembly houses (such as ASE, Amkor, STATS ChipPAC) but also offers a few

Copper Wire (Cu) Bonding Reduces Package Cost

Do you know someone that is not eager to reduce their ASIC production costs? I don’t.  Some say that redesign changes can lead to significant cost reduction, for instance – using a more advanced silicon technology node to shrink the die size. True, but this is a really big, painful

Does size matter? Understanding Wafer Size

Silicon wafers are the most essential element in the realization of ICs. The semiconductor industry had invested heavily to increase the wafer size during the last 30 years, so while foundries used to produce 1 inch wafers, today’s common wafer size is 300mm (11.8 times larger than 1 inch). There

BGA Substrate Design

Very often IC package design requires designing a BGA substrate. Substrate design and layout is very similar to any other PCB design. The difference is that the substrate size is much smaller than most of the PCBs you have seen. In this post we do something a bit unusual and

How to Obtain ASIC Turnkey Services from TSMC and GLOBALFOUNDRIES?

Pure-play foundries are offering vanilla flavor services, meaning one can buy only wafers. ASIC design, testing, packaging and supply chain services are not part of their service offering.
 
Large IDM players, who manage their own supply chain, seek this type of engagement because they prefer to own the supply

Understanding Maskset Type – MPW, MLM, MLR and Single-Maskset

Tapeout is a major milestone in every ASIC project lifecycle. It means the design phase is completed and you are ready to send out the GDSII to the fab for production.
The term “tapeout” was coined in 70’s. Historically, engineered used a magnetic tape to store all the ASIC design