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Faraday Technology Corporation (TWSE: 3035), a leading ASIC design service and IP provider, announced that its Gigabit Ethernet PHY has been silicon proven on UMC’s 28HPC+ process and is now available for new ASIC SoC designs and IP licensing. This new IP, based on 28nm node, provides the benefits of
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OTTAWA, Canada, May, 2022 – DA-Integrated is adding additional test capacity and constructing a new facility in order to accommodate continued growth. The property at 27 Iber Road is in the heart of Canada’s microelectronics sector. The new location includes a 3,200 sq ft class 10,000 clean room with class 100
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May 3, 2022 — Silex Insight, a leading provider of cryptographic IP solutions, today entered into a partnership arrangement with leading IoT security company ZAYA, who delivers a secure OS containerisation technology for microcontrollers, called ZAYA μContainers. The ZAYA μContainers can be added to Silex Insight’s eSecure Root of Trust module
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IC Insights’ 2Q Update to The McClean Report 2022 will be released in May. It presents an analysis of the marketshare of the major semiconductor suppliers excluding the pure-play foundries (Figure 1). While there is a small amount of double-counting effect due to the IDM foundry revenue included in the figures, it is
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IC Insights’ February 1Q Update to The McClean Report 2022 includes an overview of IC industry capacity and wafer start trends from 2002 through 2026. This bulletin provides a brief summary.
The volatile nature of the IC industry is reflected by large swings in annual wafer starts. Over the past five years, for
Santa Clara, CA, – April 18, 2022 – MosChip Technologies, a semiconductor and system design services company, unveils today enhanced simplex High Speed Serial Trace Probe (HSSTP) PHY macro with link layer supporting data transfer capabilities of up-to 12.5Gbps per lane in 6nm FinFET technology. MosChip has over a twenty-year track
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Faraday Technology Corporation (TWSE: 3035), leading ASIC design service and IP provider, today launched SoCreative!VI™ A600 SoC development platform implemented in Samsung Foundry’s 14LPP FinFET process technology. This platform is equipped with Faraday’s A600 SoC chip on an evaluation board and the Linux software development kit (SDK) to create a full-performance system
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Tel Aviv, Israel – March 24, 2022 – ATS Engineering, a leading Israeli test house, and ChipTest Semiconductor IC Test Company, have announced an exclusive collaboration agreement for developing test programs and test interfaces (load boards and probe cards) on the ATS’ Advantest V93000 Smart Scale platform, to support ATS
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System in Package (SiP) is a method used for bundling multiple integrated circuits (ICs) and passive components into a single package, under which they all work together. This contrasts to a System on Chip (SoC), whereas the functions on those chips are integrated into the same die.
Figure
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Wafer Level Packaging or WLP, is a type of IC packaging technology that is performed at wafer level. This means that the packaging is applied on whole wafers and wafers are diced only after the packaging is successfully competed. In wafer level packaging, the components used in assembly (such as
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