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CAST Releases First Dual LZ4 and Snappy Lossless Data Compression IP Core

press release gpt

Woodcliff Lake, New Jersey — June 27, 2025 — Semiconductor intellectual property core provider CAST today announced a new IP core that provides lossless data compression using either the LZ4 or the Snappy algorithms. It joins CAST’s existing LZ4 and Snappy decompression IP core to provide what the company believes

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VeriSilicon Expands DSP Portfolio with Silicon-Proven ZSP5000 Vision Core Series for Edge Intelligence

press release chip

Shanghai, China — June 26, 2025 — VeriSilicon (688521.SH) today released the ZSP5000 Digital Signal Processing (DSP) series IPs, which are based on its fifth-generation silicon-proven DSP architecture. This product line adopts a highly scalable and energy-efficient design, and has been deeply optimized for compute-intensive workloads such as computer vision and

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Arteris Wins “AI Engineering Innovation Award” at the 2025 AI Breakthrough Awards

News

CAMPBELL, Calif., Jun. 26, 2025 –  In a market fueled by the compute demands of AI, Arteris, Inc. (Nasdaq: AIP), a leading provider of system IP for accelerating system-on-chip (SoC) creation, today announced that it has won the “AI Engineering Innovation Award” at the 8th annual AI Breakthrough Awards conducted by the market intelligence organization AI

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eMemory’s NeoFuse OTP Qualifies on TSMC’s N3P Process, Enabling Secure Memory for Advanced AI and HPC Chips

Press Release PR

(Hsinchu Taiwan, June 26, 2025) eMemory announced that its one-time programmable (OTP) memory solution, NeoFuse, has achieved qualification on TSMC’s N3P process, an enhanced 3nm process for better power, performance and density. As eMemory’s first OTP IP qualified on the TSMC N3P process, NeoFuse OTP underscores the company’s leadership in providing

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Sofics Delivers Remarkable PPA & R Performance Near Physical Limits on TSMC 2nm Technology

press release

GISTEL, BELGIUM – June 25, 2025 – Sofics bv, a world leading solution provider specializing in physical layout and design, with a focus on the built-in robustness of integrated circuits that demand superior power, performance, and area (PPA), today announced the silicon validation of its IP for TSMC’s cutting-edge

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Creonic’s DVB-S2 and DVB-S2X IP Cores Now Support the New DVB-NIP Standard

press release

Creonic’s DVB-S2 and DVB-S2X IP cores now include support for the new DVB-NIP standard on physical layer — an important step toward seamless integration of satellite and IP-based network technologies.
 
The DVB-NIP standard is designed to facilitate the native transport of IP over satellite networks, extending the capabilities of DVB-S2X by streamlining packet-based

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