Principal Digital ASIC Design Engineer

K2 is a pioneering space startup focused on developing the largest and highest-power satellites ever flown, backed by significant investment and contracts. The company aims to revolutionize satellite technology for various missions, leveraging advancements in heavy-lift launch vehicles to create a new class of spacecraft capable of operating in extreme environments. K2 is seeking a Principal Digital ASIC Design Engineer to join their innovative team and contribute to the design of advanced wireless SoCs for their cutting-edge satellite systems.

Responsibilities:

• Own the architecture, microarchitecture, RTL implementation, and integration of key digital blocks in wireless SoCs.
• Collaborate with system architects to translate high-level DSP algorithms into efficient hardware implementations.
• Drive end-to-end development of DSP systems (e.g., filters, beamformers, FFT/IFFT engines).
• Convert chip specifications into RTL using internal and external IPs.
• Design and develop RTL for interfaces, power management, clocking, reset, test & debug.
• Partner with analog/mixed-signal teams to define digital-analog interfaces, calibration engines, and control logic.
• Optimize designs for power, performance, and area (PPA) and support timing closure through synthesis and backend collaboration.
• Lead or contribute to verification planning and validation of complex digital subsystems.
• Participate in chip bring-up and lab validation of complex digital subsystems.
• Support your product through production and spaceflight.
• Act as a technical leader and subject-matter expert, mentoring team members.

Qualifications:

• B.S. or M.S. in Electrical Engineering, Computer Engineering, or related field.
• 10+ years of relevant industry experience in digital ASIC design, with significant ownership of complex subsystems.
• Proficiency in RTL design (SystemVerilog or Verilog), synthesis, and linting tools.
• Experience in micro-architecture definition from architecture guidelines and model analysis.
• Experience in closing full-chip and subsystem timing working with synthesis and static analysis teams.
• Experience with DFT tools for scan and BIST insertion.
• Solid understanding of SoC design flows including clock/power domain crossing, timing constraints, and formal verification.
• Experience developing and integrating DSP blocks for wireless communication (e.g. OFDM, MIMO, channel estimation, DFE, etc.).
• Strong experience with EDA tools for design, synthesis, static timing analysis, and power analysis (e.g. Synopsys, Cadence, Siemens tools).
• Strong debugging, problem-solving, and communication skills.

Skills:

• Prior experience in wireless SoC development (e.g. cellular, Wi-Fi, satellite, or mmWave systems) and successful tapeouts in advanced design nodes.
• Design experience in datapath, flow control, arbitration, FIFO, DMA, IOMMU, SoC bus architecture, ARM's AXI/AHB bus architecture & protocols, serial interfaces such as SPI, I3C, UART.
• Familiarity with DSP algorithm modeling (MATLAB, Python, or C++) and converting models into RTL.
• Experience working with FEC, baseband PHYs, or digital beamforming architectures.
• Knowledge of digital calibration and control of RF/mixed-signal front ends.
• Exposure to hardware-software co-design and embedded process integration.
• Experience working in cross-functional, geographically distributed teams.