ASIC Engineering Technical Leader

Join Acacia, part of Cisco, as an ASIC Engineering Technical Leader focused on Design-for-Test (DFT) solutions for next-generation optical communications products. This role involves leading the development of DFT architectures and ensuring the readiness of ASIC designs for high-speed optical interconnects.

Responsibilities:

• Lead the implementation of DFT architectures including scan insertion and memory BIST using Siemens Tessent or Synopsys tools.
• Generate ATPG test patterns for various fault models and support post-silicon testing and validation.
• Evaluate design readiness for scan insertion through RTL and physical design DRC tools.
• Integrate and verify DFT fabrics and IP within subsystems.
• Perform simulation runs and debug gate level simulations.
• Develop test scripts and automate processes using programming languages like Python, Tcl, or C++.

Qualifications:

• Bachelor's degree with 8 years of experience, Master's with 6 years, or PhD with 3 years of experience in ASICs.
• Experience in scan insertion and DFT setup, integration, and validation.

Skills:

• Strong knowledge of DFT architectures including scan insertion and BIST.
• Experience with ATE testers and test teams.
• Proficiency in RTL design and debugging.
• Ability to solve complex problems, including clock domain crossings.
• Familiarity with advanced silicon processes for high speed and low power consumption.
• Strong implementation skills using Verilog/System Verilog.