DFT Engineer

Broadcom's ASIC Product Division is seeking a DFT Engineer for its San Jose, California Development Center. The role involves working on various phases of SoC DFT activities, including test insertion, verification, pattern generation, and yield improvement, while collaborating with the Physical Design & STA team. Candidates should be proficient in coding with languages such as TCL, PERL, RUBY, PYTHON, or C++.

Responsibilities:

• Understand Broadcom and customer DFT feature requirements and define appropriate DFT specifications for ASICs.
• Implement DFT techniques including Scan, MBIST, TAP, LBIST, IO, SerDes, and other I/P DFT integrations.
• Generate, verify, and debug test vectors before tape release.
• Validate and debug test vectors on ATE during the silicon bring-up phase.
• Assist with silicon failure analysis, diagnostics, and yield improvement efforts.
• Automate DFT and test vector generation flows.

Qualifications:

• Bachelor's degree in Electrical/Electronic/Computer Engineering with 2+ years of relevant industry experience, or a Master's degree in the same fields.

Skills:

• Exposure to DFT flows.
• Experience in Verilog coding, testbench generation, and simulation.
• Memory BIST insertion and verification experience on embedded memory types (SRAM, CAM, eDRAM, ROM).
• Basic knowledge of Test-STA and constraints.
• Strong background in IEE1687, IJTAG, ICL, and PDL.
• Ability to work in a multi-disciplined, cross-department environment.
• Solid knowledge of analog and digital circuit design and device physics fundamentals.
• Good understanding of silicon processing, logical and physical synthesis, and transistor reliability principles.
• Excellent problem-solving, debugging, root cause analysis, and communication skills.
• Experience working on ATE is a plus.