ASIC & FPGA Design Engineer Sr

The Senior ASIC & FPGA Design Engineer will lead the Command Launch Assembly (CLA) FPGA team within Missiles & Fire Control (MFC), focusing on developing reliable FPGA hardware for the Next Generation Short Range Interceptor (NGSRI). This role involves overseeing the entire FPGA lifecycle, from architecture to documentation, while mentoring junior engineers and collaborating with cross-functional teams.

Responsibilities:

• Define FPGA architecture and draft design specifications.
• Write clean RTL in VHDL/Verilog/SystemVerilog to meet performance, power, and reliability targets.
• Develop synthesis, place and route, and timing closure strategies for FPGA families.
• Build comprehensive test plans, simulation models, and verification environments (UVM, SystemC, Python).
• Lead hardware in the loop (HIL) tests, board level debugging, and subsystem integration activities.
• Translate system level performance, safety, and reliability requirements into detailed FPGA architectures.
• Conduct timing analysis, power budgeting, and device selection optimization.
• Manage configuration control with GitLab, ensuring full traceability of design artifacts.
• Produce complete design packages compliant with aerospace and Lockheed Martin standards.
• Collaborate with systems, software, hardware, mechanical, test, manufacturing, and quality teams to maintain program schedules.
• Mentor junior engineers and promote best practices in FPGA development.

Qualifications:

• Bachelor's degree in Electrical Engineering or related STEM field; Master's preferred.
• Minimum 3 years of experience in FPGA design and simulation verification.
• Proficiency in HDL programming (VHDL, Verilog, SystemVerilog).
• Experience with Xilinx/AMD toolsets (Vivado, Vitis) and UltraScale design methodology.
• Familiarity with FPGA simulation tools (e.g., Synopsys VCS).
• Strong understanding of digital design principles, including timing analysis and signal integrity.
• Experience with high-speed interfaces (AXI, Ethernet, TCP/IP, PCIe).
• Practical laboratory debug experience with high-speed test equipment.
• Familiarity with Synopsys EDA tools.
• Must be a U.S. Citizen and able to obtain a DoD Secret clearance.

Skills:

• Experience with SystemVerilog, Verilog, C/C++, MATLAB/Simulink.
• Knowledge of Synopsys Synplify, VCS, NCSim, ChipScope tool sets.
• Experience with Xilinx/AMD and MicroSemi/Microchip FPGA families.
• Understanding of NSA algorithms (e.g., AES).
• Experience managing configuration control (GitLab preferred).
• Proficient with Vivado and Vitis FPGA toolsets.
• Experience with UVM and Simulink/HDL Coder integration.
• Comfortable using digital oscilloscopes and other test equipment.
• Experience in full ASIC/FPGA lifecycle (architecture to validation).
• Strong communication and collaboration skills.
• Knowledge of networking and debugging tools (tcpdump, Wireshark).