ASIC Design Verification Engineer [Santa Clara, CA]

Qualcomm Technologies, Inc. is seeking an ASIC Design Verification Engineer to join its Engineering Group, specifically within ASICS Engineering. This role is pivotal in the verification lifecycle, from system-level concept to post-silicon support, focusing on digital power IPs and utilizing advanced verification methodologies.

Responsibilities:

• Manage the complete verification lifecycle from concept to tape out and post-silicon support.
• Develop comprehensive pre-silicon test plans for digital power IPs.
• Create testbenches using SystemVerilog-UVM and develop coverage and assertion models.
• Implement formal verification techniques for property checking.
• Learn and apply power-aware UPF verification methodologies.
• Automate processes to enhance verification efficiency.

Qualifications:

• Bachelor's degree in Science, Engineering, or related field with 2+ years of relevant experience; or a Master's degree with 1+ year; or a PhD in a related field.
• Minimum 3 years of experience in design verification using UVM and assertion-based technologies.
• Experience in verifying complex SOCs or SOC subsystems.

Skills:

• Proficiency in UVM, SystemVerilog, assertions, C++, and Python.
• Familiarity with DDR, CACHE, and SOC technologies.
• Experience with memory verification VIPs and DDR PHY.
• Exposure to firmware/driver development and formal verification techniques.