Senior ASIC Design Verification Engineer

Join the Silicon One team at Cisco as an ASIC Design Verification Engineer, where you'll contribute to innovative hardware platforms that power core Switching, Routing, and Wireless products globally. This role is pivotal in shaping the future of technology through the development of cutting-edge data center solutions.

Responsibilities:

• Drive the definition, architecture, and design of high-performance ASICs, owning complex functional areas.
• Define new verification methodologies to support advanced design architectures and develop reusable code for future projects.
• Lead design verification efforts by resolving block-level issues and participating in cluster and chip-level issue resolution.
• Architect, develop, and maintain cluster and top-level Design Verification (DV) environment infrastructure.
• Build DV environments from scratch for cluster and chip levels.
• Develop, implement, and enhance test plans and tests for cluster and chip verification using constraint-random and directed stimulus.
• Ensure comprehensive verification coverage through code and functional coverage implementation and review.
• Qualify RTL design by running Gate Level Simulations with timing annotation on netlists.
• Support design testing in emulation environments.
• Debug issues at ASIC, software, and systems levels, assisting in lab bring-up and post-silicon validation.

Qualifications:

• Bachelor's degree in Computer, Electrical, or Electronics Engineering with 7 years of relevant experience, or a Master's degree with 4 years of relevant experience focused on ASIC design and verification.
• Experience in Object-Oriented Programming (OOP) concepts, System Verilog, or UVM methodology.
• Experience leading verification teams or managing project assignments.
• Proficiency in scripting using Perl and/or Python.

Skills:

• Experience with forwarding logic, parsers, or P4.
• Familiarity with emulation platforms such as Veloce, Palladium, Zebu, or HAPS.
• Knowledge of formal verification tools (e.g., IEV or VC Formal).
• Domain knowledge in protocols such as PCIe, CXL, Ethernet, RDMA, DDR, or TCP.