ASIC Design Engineer – SoC Interconnect, Cache & Memory Systems

Qualcomm Technologies, Inc. is seeking talented ASIC Design Engineers to join its Engineering Group, focusing on delivering industry-leading System-on-Chip (SoC) solutions. The role involves collaborating with various teams to develop high-performance, power-efficient silicon solutions for smartphones, PCs, automotive platforms, and emerging technologies.

Responsibilities:

• Develop microarchitecture definitions and design specifications for complex SoC subsystems.
• Design, implement, and validate RTL for SoC interconnects, cache controllers, memory subsystems, and DDR memory controller components.
• Collaborate with system architects to evaluate hardware feasibility of new features, algorithms, and performance requirements.
• Optimize designs for performance, power, area, timing, and scalability.
• Work closely with verification teams to develop test plans, review coverage, debug issues, and achieve design quality goals.
• Support synthesis, timing closure, power analysis, gate-level simulations, and physical design activities.
• Participate in system-level integration and debugging throughout the product development cycle.
• Investigate and resolve pre-silicon and post-silicon issues.
• Contribute to C/C++ modeling, design methodologies, and process improvements that enhance engineering productivity and design quality.
• Collaborate across cross-functional teams to successfully deliver silicon for production.

Qualifications:

• Bachelor's, Master's, or PhD in Electrical Engineering, Computer Engineering, Computer Science, or a related field.
• 0-4 years of industry experience or relevant academic experience in ASIC/SoC design.
• Experience or coursework in Verilog and/or SystemVerilog RTL design, Computer Architecture, ASIC design methodologies, Digital logic design, C, C++, and/or Python programming.
• Strong analytical and problem-solving skills.
• Excellent communication and collaboration skills.

Skills:

• SoC interconnects and on-chip communication fabrics
• Cache and memory subsystem design
• DDR/LPDDR memory controller architecture and design
• ARM or x86 processor architectures and bus protocols
• RTL development for CPUs, cache controllers, or memory controllers
• Low-power design methodologies
• Functional verification and coverage-driven verification techniques
• Synopsys synthesis tools and ASIC implementation flows
• Timing closure, physical design support, and power optimization
• Silicon bring-up and post-silicon debug