Sofics Delivers Remarkable PPA & R Performance Near Physical Limits on TSMC 2nm Technology

GISTEL, BELGIUM – June 25, 2025 – Sofics bv, a world leading solution provider specializing in physical layout and design, with a focus on the built-in robustness of integrated circuits that demand superior power, performance, and area (PPA), today announced the silicon validation of its IP for TSMC’s cutting-edge 2nm technology, which adopts nanosheet transistor structure. This marks a significant milestone in the long-standing partnership between Sofics and TSMC, and underscores Sofics’ continued commitment to shorter times-to-market and unique value for leading applications in the world’s most advanced semiconductor process nodes.

As a key and long-standing partner of TSMC’s Open Innovation Platform® (OIP) ecosystem and a member of TSMC OIP Design Center Alliance (DCA) and IP Alliance since 2010, Sofics has collaborated with TSMC from an early stage to validate its IP on TSMC’s 2nm process. Through continued layout and design innovation, higher PPA and robust performance was achieved in on-chip ESD devices and interface circuits. Key results include:

“ Our collaboration with TSMC OIP ecosystem partners like Sofics on our most advanced technologies is critical for enabling our joint customers to create next-generation designs for AI and HPC innovations. We will continue to work closely with our OIP partners to deliver competitive advantages in performance and power-efficiency for our customers” — Lluis Paris, senior director of ecosystem and alliance management division, TSMC North America.

Sofics’ collaboration with TSMC in early silicon validation ensures fabless designers can access pre-verified, high-performance IP that accelerates time-to-market, reduces risk, and cuts costs — especially vital for ultra-low power and chiplet-based architectures.