Snap Inc. is seeking a Design Verification Engineer to join the Spectacles Team, focusing on the development of display Integrated Circuits for augmented reality. In this role, you will collaborate with a multi-disciplinary team, working closely with digital design, analog logic, software, and verification engineers. Your responsibilities will include developing UVM-based and assertion-based testbenches, executing verification test plans, and utilizing the Siemens Questa toolset for verification and debugging tasks. The ideal candidate will possess a strong background in UVM and SystemVerilog, along with extensive experience in ASIC Design Verification. Proficiency in scripting and automation languages such as TCL, Python, and Shell scripts is essential. A minimum of 10 years of relevant experience, along with a BSEE or MSEE, is required. Familiarity with video and display systems, as well as a self-starter attitude, will contribute to your success in this innovative environment.
