{ mission: { description: At Palo Alto Networks®, our mission is to be the cybersecurity partner of choice, safeguarding our digital way of life. We envision a world where each day is safer and more secure than the last, and we are committed to innovating and disrupting the status quo in cybersecurity. }, work_environment: { description: We believe that collaboration thrives in person, which is why most of our teams work from the office full time, with flexibility when needed. This approach fosters real-time problem-solving, strengthens relationships, and enhances the precision that drives exceptional outcomes. }, job_role: { description: Join our ASIC team to contribute to the digital logic that powers our next-generation firewall platforms. You will take ownership of module design from specification through silicon bring-up, collaborating with top-tier verification and physical-design engineers to achieve ambitious performance, power, and schedule objectives. }, responsibilities: { description: [ Write clear design and micro-architecture specifications., Design SystemVerilog RTL that meets area, performance, and power targets., Verify your blocks using simulation, emulation, formal methods, and silicon bring-up., Collaborate with verification engineers to debug complex scenarios, close coverage, and implement design-for-debug features., Partner with physical-design teams to review synthesis/timing reports, rewrite RTL to close critical paths, and consult on floor-planning for congestion and routability., Innovate by piloting AI-driven design or verification flows that mitigate schedule risks. ] }, qualifications: { required: { education: BS in Electrical Engineering, Computer Engineering, or Computer Science ., experience: 10 years of front-end ASIC design ownership with a track record of shipping 2 chips to mass production., skills: [ Solid experience with PCIe core integration and lab validation., Expertise in SystemVerilog RTL., Proficiency in scripting languages such as Python, C/C++, Perl, bash, or tcsh. ], strengths: [ Defining micro-architecture from high-level requirements., Expertise in datapath design for complex synchronous/asynchronous digital logic., Debugging across simulation, emulation, and silicon., Analyzing timing, power, and area reports and driving necessary fixes., Excellent leadership, collaboration, and communication skills. ] }, preferred: { description: Knowledge in networking or cybersecurity domains, experience with DDR5 memory, Ethernet , or search-algorithm accelerators, formal-verification ownership, and hands-on silicon validation and lab bring-up are considered advantageous. } } }
