May 26th, 2026 — Intel is already looking beyond its upcoming 18A and 14A process technologies, with early development reportedly underway for future 10A and 7A nodes. The update signals that Intel Foundry wants to show customers a long-term advanced-node roadmap extending into the next decade, even as the company continues to work through the difficult transition from an internal manufacturing model to a competitive foundry business.
According to recent industry reports, Intel CEO Lip-Bu Tan confirmed that development activity has begun for 10A and 7A, while Intel 14A remains on track for a major process design kit milestone. Intel has reportedly already provided a 0.5 version of the 14A PDK to customers, with a more mature 0.9 PDK targeted for external customers in October 2026. Risk production for 14A is expected in 2028, followed by high-volume manufacturing in 2029.
For fabless semiconductor companies, the announcement is important not only because of the future nodes themselves, but because it shows how Intel is trying to build confidence around its foundry roadmap. Advanced chip projects often require several years of planning, architecture work, IP readiness, EDA enablement, test-chip validation and customer engagement before production begins. Foundry customers therefore need more than one node option; they need visibility into a multi-generation roadmap.
While 10A and 7A are longer-term technologies, Intel 14A is the near-term node to watch. Intel 14A is expected to be Intel’s first major process technology to use High-NA EUV lithography in volume manufacturing. High-NA EUV is designed to improve patterning capability for smaller geometries and is one of the key technologies expected to support continued transistor scaling at the most advanced nodes. Intel’s own foundry materials describe 14A as including High-NA EUV, RibbonFET improvements, backside power delivery and Turbo Cells for performance optimization.
The PDK milestone is particularly important. A PDK is the bridge between the manufacturing process and the chip design ecosystem. It provides designers with the device models, design rules, verification decks, parasitic information and libraries needed to start real product development. Early PDK versions allow customers to evaluate the technology and begin feasibility work, but a more mature PDK is typically needed before serious tapeout planning can begin.
The reported 0.9 PDK release in October 2026 is therefore a critical step for customer adoption. It does not mean the process is ready for mass production, but it does mean the design ecosystem is expected to become mature enough for deeper customer engagement. TheElec also reported that Intel has already distributed the 0.5 PDK and is targeting the 0.9 PDK for external customers in October.
Intel 14A is more than just another node in Intel’s roadmap. It is likely to be a major test of Intel Foundry’s ability to win external customers at the leading edge.
Intel has invested heavily in rebuilding its manufacturing competitiveness. Its 18A process introduced RibbonFET gate-all-around transistors and PowerVia backside power delivery, both of which are important technologies for advanced logic scaling. Intel 14A is expected to take the next step with High-NA EUV and further improvements to performance and power efficiency. Intel has previously indicated that 14A could deliver a 15–20% performance-per-watt improvement or 25–35% lower power compared with 18A, depending on design choices and implementation.
However, advanced-node development is extremely expensive. High-NA EUV tools are costly, and the economics of a leading-edge foundry node depend heavily on volume. This means Intel needs committed customers, not only technical progress. Without strong external demand, the business case for 14A and future nodes becomes more difficult.
This is why the roadmap matters. A customer considering Intel Foundry for a high-performance computing, AI accelerator, networking processor or advanced SoC project must believe that Intel can support not just one tapeout, but a multi-generation product plan.
Intel’s early work on 10A and 7A should be viewed as a strategic signal. These nodes are not near-term manufacturing options for customers. Instead, they represent Intel’s attempt to show that its foundry ambitions extend beyond 18A and 14A.
The naming suggests future angstrom-class nodes that would come after 14A, likely targeting the 2030s. At that stage, the industry will be dealing with even more complex scaling challenges, including transistor architecture, interconnect resistance, power delivery, lithography cost, yield learning and advanced packaging integration.
For Intel, 10A and 7A development also shows that High-NA EUV is not a one-node experiment. If 14A becomes the first major High-NA EUV node, then 10A and 7A would likely build on that manufacturing foundation. Intel has already positioned High-NA EUV as a key technology for future process scaling.
Intel’s roadmap must be understood in the context of the broader foundry market. TSMC remains the dominant player in advanced logic manufacturing, while Samsung continues to compete in gate-all-around and leading-edge foundry services. Intel is trying to become a credible third option at the most advanced nodes.
Intel 14A’s reported 2029 volume production timeline places it near the expected timeframe for TSMC’s A14-class technology, although direct comparisons between process nodes are never simple. Node names no longer correspond directly to physical gate length or a single dimension. Actual competitiveness depends on performance, power, density, SRAM scaling, yield, design ecosystem readiness, IP availability, packaging options and cost.
For customers, the key question is not simply whether Intel 14A looks strong on paper. The more important question is whether Intel can deliver predictable PDKs, stable design rules, reliable yield ramps and a foundry customer experience comparable to established players.
For fabless companies, PDK maturity can determine how early a chip design team is willing to commit resources. A process may look promising, but if the PDK is unstable, design teams face risks such as rule changes, model updates, timing uncertainty and rework late in the design cycle.
This is especially important for large chips. AI accelerators, server CPUs, GPUs and networking ASICs often require massive design investments. These products depend on proven IP blocks, advanced packaging, high-speed interfaces, robust power delivery and extensive physical verification. A small delay or design-rule change can translate into major cost and schedule impact.
Therefore, Intel’s October 2026 PDK 0.9 target is not just a technical milestone. It is a commercial milestone. It is the point where potential customers can better judge whether 14A is becoming a real foundry platform.
Process technology alone is no longer enough to win at the high end of the semiconductor market. Many advanced products now rely on chiplets, 2.5D packaging, high-bandwidth memory integration and heterogeneous integration.
Intel has strong internal experience with advanced packaging technologies, and this could become an important part of its foundry offering. For customers building AI and high-performance computing products, the combination of leading-edge logic, backside power delivery, High-NA EUV and advanced packaging could be attractive — provided that the full ecosystem is ready.
In practice, the winning foundry platform will be the one that combines process performance with design enablement, packaging, IP, yield, cost and supply assurance.
Intel’s announcement highlights several important industry trends:
First, the advanced-node roadmap is stretching further into the future. Customers are already thinking about technologies that may not reach volume production until the end of this decade or beyond.
Second, High-NA EUV is moving from research and early adoption toward practical manufacturing planning. Intel is positioning 14A as a key entry point for this transition.
Third, foundry competition is becoming more strategic. Governments, hyperscalers, AI chip companies and fabless semiconductor firms all want more manufacturing options, but they also need confidence that those options are technically and commercially viable.
Finally, PDKs and ecosystem readiness are becoming as important as transistor announcements. A node cannot succeed only through technology claims; it must be usable by real customers with real product schedules.
Intel’s early development work on 10A and 7A shows that the company is trying to build a long-term foundry roadmap beyond 18A and 14A. However, the more immediate test is Intel 14A. The planned October 2026 PDK 0.9 release, followed by expected risk production in 2028 and volume manufacturing in 2029, will be important milestones for Intel’s foundry ambitions.
If Intel can deliver a mature PDK, demonstrate competitive performance and yield, and secure meaningful external customers, 14A could become a major step in making Intel Foundry a serious player in leading-edge manufacturing. If not, the roadmap to 10A and 7A may remain more strategic than commercial.
For semiconductor companies, the message is clear: the leading-edge foundry market is entering a new phase. Process technology, PDK maturity, advanced packaging and long-term supply strategy will all play a critical role in choosing the right manufacturing partner for next-generation chips.
