Published Date: January 20, 2026
Qualcomm, Santa Clara, CA
Job Description:
Qualcomm Technologies, Inc. is seeking an experienced ASIC Engineer to join its Engineering Group, focusing on ASICS Engineering. This role involves working with cutting-edge sensor technologies across various applications, including smartphones, automotive, IoT, and consumer electronics. The position encompasses the entire ASIC design process, from specification to layout, and requires collaboration with cross-functional teams to develop high-performance digital sensor subsystems for mobile applications.
Responsibilities:
- Define, model, design, optimize, verify, validate, implement, and document IP development for high-performance products.
- Create advanced architectures and circuit specifications based on system-level requirements.
- Collaborate with software and hardware architecture teams to execute implementation strategies that meet system requirements.
- Evaluate complex process flows from high-level design to synthesis and verification.
- Utilize tools for advanced architecture and design of complex blocks/SoC or IC Packages.
- Write and review technical documentation for EDA/IP/ASIC projects.
- Architect, design, and implement digital sensor hardware for ASIC SoC.
- Debug, verify, and optimize designs with test vectors.
- Conduct ASIC synthesis and static timing analysis for timing-closed designs.
- Estimate power and implement low-power design strategies.
- Collaborate with Software and Systems Engineering teams.
- Adhere to Qualcomm’s processes for RTL and netlist releases.
- Automate workflows using Python and improve team efficiency.
- Participate in project reviews and documentation.
Qualifications:
- Bachelor's degree in Science, Engineering, or related field with 4+ years of relevant experience; OR a Master's degree with 3+ years; OR a PhD with 2+ years of experience in ASIC design, verification, validation, or integration.
Skills:
- Proficient in ASIC RTL Synthesis, LEC, Power Extraction tools, Primetime, and RTL Linting tools.
- Experience with ASIC ECO flow and RTL sanity tools for Design Rule Checking and Clock Domain Crossing checks.
- Familiarity with C++/SystemC and High Level Synthesis is a plus.
- Strong analytical skills and ability to work in a dynamic team environment.
- Excellent written and verbal communication skills.
- Strong interpersonal skills and a good team player.