Senior ASIC Timing Engineer

NVIDIA is seeking Senior ASIC Timing Design Engineers to join its Networking Silicon engineering team, focusing on the development of high-speed communication devices. This role involves driving physical design and timing for advanced DPUs and SoCs, contributing to innovative chip design in a supportive and diverse environment.

Responsibilities:

• Drive physical design and timing of high-frequency and low-power DPUs and SoCs at various levels.
• Analyze and optimize design constraints and synthesis parameters to meet performance, power, and area targets.
• Oversee frontend and backend implementation from RTL to gds2, including synthesis, equivalence checking, and timing convergence.

Qualifications:

• BS in Electrical or Computer Engineering with 8 years of experience or MS with 4+ years in Synthesis and Timing.
• Hands-on experience in full-chip/sub-chip Static Timing Analysis (STA) and timing constraints management.
• Expertise in timing path analysis and fixing through ECOs, including crosstalk and noise analysis.

Skills:

• Proficiency in physical design optimization techniques such as placement, routing, and logic restructuring.
• Background in logic synthesis and logical equivalence checking (LEC).
• In-depth knowledge of EDA tools like Synopsys PrimeTime or Cadence Tempus.
• Proficiency in Python, Tcl, and Make for automation and scripting tasks.