Senior ASIC Timing Engineer

NVIDIA is seeking a motivated ASIC Timing Engineer to join its innovative team, contributing to the development of cutting-edge technology in AI and computing. With over 25 years of experience in transforming computer graphics and gaming, NVIDIA is at the forefront of the next era of computing, where GPUs serve as the brains of advanced systems. The company values diversity and fosters a supportive environment for its employees.

Responsibilities:

• Drive timing analysis and closure for NVIDIA’s GPUs, CPUs, DPUs, and SoCs at various levels.
• Collaborate with cross-functional teams to create timing constraints and implement timing closure strategies.
• Contribute to innovative projects by improving timing convergence flows in partnership with methodology teams.

Qualifications:

• BS in Electrical or Computer Engineering with 5 years of experience, or MS with 2 years of experience in Timing and STA.
• Hands-on experience in full-chip/sub-chip Static Timing Analysis (STA) and timing convergence.
• Expertise in timing path analysis and fixing through ECOs, including crosstalk and noise analysis.
• Knowledge of physical design and optimization techniques to enhance timing and power.

Skills:

• In-depth knowledge of industry-standard STA and timing convergence tools.
• Experience with deep sub-micron process nodes and timing modeling.
• Background in domain-specific STA for GPUs, CPUs, DPUs, or SoCs.
• Understanding of DFT logic and timing closure for various modes.
• Experience in methodology and flow development, including automation.