Low Power ASIC Engineer – New College Grad 2026

NVIDIA is seeking a Low Power Design/Verification ASIC Engineer for new college graduates in 2026. This role is part of the rapidly growing team focused on developing energy-efficient GPU and SOC architectures, contributing to innovative solutions across various sectors including AI, Automotive, GeForce, and Mobile products.

Responsibilities:

• Collaborate with Low Power Architecture, Design, and Software teams to understand next-generation features.
• Architect and develop testbench, infrastructure, and test plans to verify power management solutions for NVIDIA products.
• Contribute creative ideas to enhance power-aware design verification methodologies and influence EDA vendors for improved simulation and debugging efficiencies.

Qualifications:

• Recently completed a BS, MS, or PhD in Electrical or Computer Engineering or equivalent experience.
• Understanding of low power design techniques such as multi VT, clock gating, power gating, block activity power, and dynamic voltage-frequency scaling (DVFS).
• Good understanding of processor architecture, with GPU knowledge being a plus.

Skills:

• Experience with Incisive Low-Power or Synopsys VCS NLP.
• Strong debugging skills and experience with Verdi.
• Fluency in Verilog and SystemVerilog, with an understanding of UVM.
• Scripting abilities in Python or PERL, and knowledge of C or C++ is a plus.