Senior ASIC Power Engineer, Machine Learning Accelerators

Join Google's AI and Infrastructure team as a key contributor to the development of cutting-edge Tensor Processing Units (TPUs) that power AI/ML applications. This role focuses on enhancing power efficiency in silicon design, driving innovative power optimization techniques, and collaborating with cross-functional teams to redefine computing capabilities.

Responsibilities:

• Contribute to design power modeling and drive convergence to power goals.
• Investigate, specify, and deploy architectural and microarchitectural power optimization techniques.
• Define best practices and methodologies to achieve low-power Register-Transfer Level (RTL) designs.
• Collaborate with cross-functional software and system teams to create novel power management architectures to meet power goals.

Qualifications:

• Bachelor's degree in Electrical Engineering, Computer Engineering, Computer Science, or a related field, or equivalent practical experience.
• 8 years of experience in silicon design or architecture (e.g., logic design, power architecture, performance, or SoC design).
• Experience with power design, power modeling, power architecture, or power reduction methodologies/techniques.
• Master's degree or PhD in Electrical Engineering, Computer Engineering or Computer Science, with an emphasis on computer architecture (preferred).
• Experience defining and implementing chip-wide power management architectures and designs (preferred).
• Understanding of modern power and thermal management techniques at both the silicon and system levels (preferred).

Skills:

• Ability to solve open-ended power and performance problems under ambiguity.
• Strong background in modeling and optimizing chip power.
• Understanding of system-level power considerations and tradeoffs.