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The Ultimate Guide to Clock Gating

Clock Gating is defined as: “Clock gating is a technique/methodology to turn off the clock to certain parts of the digital design when not needed”.
 
The Need for Clock Gating
 
With most of the SoCs heavily constrained by power budgets, it is of utmost importance to reduce power

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2020 Global Silicon Revenue Remains Stable as Wafer Area Shipments Edge Up Despite COVID-19 Disruption

market research

ILPITAS, Calif., Feb. 2, 2021 /PRNewswire/ — Worldwide silicon wafer area shipments in 2020 increased while revenue remained unchanged from 2019 at $11,170 million, the SEMI Silicon Manufacturers Group (SMG) reported in its year-end analysis of the silicon wafer industry. Silicon shipments totaled 12,407 million square inches (MSI), compared to 11,810 MSI shipped in

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AnalogX Announces World’s Lowest Power SERDES IP in 7nm and 6nm and Expansion Plan

News

AnalogX, the leading provider of multi-standard connectivity SerDes IP solutions, today announces the availability of its silicon-proven 7nm & 6nm SERDES. AnalogX is the market leader in low-power SERDES IP, serving the chiplet and chip-interconnect market with 16nm, 12nm, and now 7 nm & 6 nm technology nodes. The company also

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HDL Design House Partners with Marketing Platform AnySilicon

news

AnySilicon, the leading marketplace for ASIC service providers, announced today that HDL Design House, a leading-edge digital, analog, and back-end design and verification services provider, has joined AnySilicon to promote its design services. As part of the AnySilicon platform, HDL Design House will gain access to a full range of

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Webinar – High End Electronics meets Optics

AEMtec GmbH located in Berlin Germany provides a new 2021 Eight Session Webinar Series “Next Level of Technology – High End Electronics meets Optics”. Launch of webinar series in February. New industry trends, technology portfolio, implementation strategies as well as already successfully generated applications will be shown. The participant receives the

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Protocol and Interface Agnostic Universal D2D Controller for HPC and Chiplets

Demand for die-to-die and chip-to-chip interfaces has been growing steadily in the past few years due to new applications in cloud/data centers, AI (training and edge applications), and High-Performance Computing (HPC). The demand is driven by the requirements of high throughput, low latency and low power in these applications. Advances in packaging technology are further helping the

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