70 % of ASIC design goes in verification and 70 % of verification goes in debugging.
Planning for the debugging goes a long way. Feature by feature the way we architect the test bench pay some attention as to how will it be debugged. This strategy will pay back
Application Specific Integrated Circuits, ASICs, typically conjure up the notion of massively complex logic chips containing tens or hundreds of thousands (even millions) of transistors configured to solve a customer’s unique set of problems. Unlike multi-function standard product ICs such as a micro-controller that can find its way into
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AnySilicon is operating a truly unbiased semiconductor blog focused on ASIC design and manufacturing topics. We welcome individuals and companies to take part in our knowledge ecosystem and submit technical or marketing articles in the following areas:
IC design
IC verification
IP Cores
Wafer technology
Packaging/assembly
Production testing
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The performance of a system depends heavily on the communication speed between integrated circuits, which is constrained by the power delivery networks (PDNs). The disruption between the power and ground planes based on the low target impedance concept induces return path discontinuities during data transitions, which create displacement current sources
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This is the second part of my “Beyond RTL” series, where I examine alternatives to Register Transfer Level (RTL). The first part talks mostly about High-Level Synthesis, its genesis, and the state of the art of free and commercial tools that transform C/C++/SystemC to RTL. I highlighted the fundamental limitations that these
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Let’s say for a minute that you believe that it is finally time to drop RTL (maybe it was my previous post that convinced you). What can I say? I’m glad! You now have to pick among several competing technologies, each with its pros and cons, each of course claiming to be the best,
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