Author Archives: anysilicon

Name: anysilicon

Pure-Play Semiconductor Foundry Growth Is At <40nm Process Nodes

growth

IC Insights has just released its September Update to The McClean Report.  This 32-page Updateincludes a detailed look at the pure-play foundry market and an analysis of the historical DRAM price-per-bit trends.  Shown below is an excerpt from the Update that examines the IC technology trends in the pure-play foundry market.
 
In 2017, the 7% increase

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CoreHW accelerates growth – Panostaja invests in CoreHW by purchasing a majority shareholding

Investment budget local government

On Friday 15th September, CoreHW has signed an agreement on selling the shares in CoreHW to Panostaja Plc. After the transaction Panostaja will own 63 per cent of the new group to be formed through the transaction.
 
Panostaja is an investment company developing Finnish SMEs in the role of an

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AFuzion and HDL Design House Joint Webinar: Optimizing DO-254: October 4, 2017, 4 pm CEST

Aeroplane

Belgrade, Serbia – September 19th, 2017 – AFuzion, the safety-critical systems and certification company and HDL Design House, provider of digital, analog, and back-end design and verification services and products in numerous areas of SoC, will host a joint webinar on DO-254 best practices and verification optimization for avionics hardware

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Fabless Silicon Manufacture: Should Unit Cost Always Be Minimised?

I’m going to assume that low cost is not the main value proposition of your product: I’ll assume that it addresses an existing or emerging market in a way that could be summarised as “better”. But it will have a manufacturing cost associated with it, which will be determined by

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Addressing Clock Tree Synthesis (CTS) Challenges in SoC Designs

wafer

Clock tree synthesis (CTS) plays an important role in building well-balanced clock tree, fixing timing violations and reducing the extra unnecessary pessimism in the design. The goal during building a clock tree is to reduce the skew, maintain symmetrical clock tree structure and to cover all the registers in the

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Open-Silicon Completes Successful Silicon Validation of High Bandwidth Memory (HBM2) IP Subsystem Solution

Open-Silicon, a system-optimized ASIC solution provider, today announced it has successfully completed silicon validation of its High Bandwidth Memory (HBM2) IP subsystem in TSMC’s 16nm FinFET technology in combination with TSMC’s CoWoS® 2.5D silicon interposer technology and HBM2 memory. This full IP subsystem solution includes an HBM2 controller, PHY and

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