Category Archives: ASIC Design

Understanding SoC Clock Design

July 05, 2019, anysilicon

Clock is the heart of synchronous digital systems. All the events in an SoC are controlled by the active edge of the clock and clock frequency is often synonymous with throughput and performance. The distribution of clock is an interesting problem involving a plethora of design trade-offs. Designers need to

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HDL Design House Adds New Representative in Europe

June 11, 2019, anysilicon

Belgrade, Serbia – June 11th, 2019 – HDL Design House, provider of digital, analog, and back-end design and verification services and products in numerous areas of SoC and complex FPGA designs, today announced the appointment of a new sales representative, Mr Wim Rijlaarsdam, for the territory of Belgium, the Netherlands and Israel. Read More

Overview and Types of Capacitors in ASIC Design

June 08, 2019, anysilicon

On-chip capacitors are a critical element in analog and mixed signal ASIC designs and playing a key role in helping engineers reach target performance.  On-chip capacitors are limited in their quality and size and often introducing design challenges where engineers need to compromise capacitor type, chip cost and performance. This

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Marvell to Acquire Avera Semi (GF), Creating an Infrastructure ASIC Powerhouse

May 21, 2019, anysilicon

Marvell (NASDAQ: MRVL) today announced it has entered into definitive agreements to purchase Avera Semiconductor, the Application Specific Integrated Circuit (ASIC) business of GLOBALFOUNDRIES. This acquisition brings together Avera Semi’s leading custom design capabilities with Marvell’s advanced technology platform and scale, creating a leading ASIC supplier for wired and wireless

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Faraday Geared Up for Data Communication Applications in ASIC Development

May 21, 2019, anysilicon

Faraday Technology Corporation (TWSE: 3035), a leading ASIC design service and IP provider, today announced its achievement in delivering more than 10 successful projects in the Data Communication market. These projects, implemented primarily on UMC 28nm HPC and 40nm LP, cover applications such as access, aggregation switches, server adaptors, and

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IC Layout – an Overview

May 08, 2019, anysilicon

This article provides an overview and description of a typical IC layout process. Its describes the various steps within IC layout and the relationship between each step.
IC layout refers to the backend design cycle. If there’s just one aspect that distinguishes the backend design from frontend design, then

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