Category Archives: ASIC Design

Join Live Webinar on the Proven Recipe for Ultra-Low-Power SoC

November 10, 2016, anysilicon


In our connected and mobile world, IC designers are striving to save µA or even nA of power consumption to extend battery usage without recharge. IoT applications bring the need for LP to new heights involving the adoption of more complex SoC architectures based on multiple power domains, which also

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asicNorth Announces a Development Ecosystem to streamline the creation of mixed-signal IoT SoC’s

October 20, 2016, anysilicon


Williston, VT October 17, 2016:  asicNorth announced today they have created a complete development ecosystem specifically targeted toward custom “Internet of Things” (IoT) devices.  The asicNorth “IoT Design EcoSystem” is formed by linking key partners in system design, semiconductor design and process technology areas.  Joining asicNorth are SoC Solutions, Faraday

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Introduction to ASIC Design Flow

October 10, 2016, anysilicon


Today, ASIC design flow is a mature process with many individual steps. ASIC design flow process is the backbone of every ASIC design project. To ensure design success, one must have: a silicon-proven ASIC design flow, a good understanding of the ASIC specifications and requirements, and an absolute domination over

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Understanding Standard Cell Characterization

October 06, 2016, anysilicon


Cell characterization is a process of analyzing a circuit using static and dynamic methods to generate models suitable for chip implementation flows.
Why is cell characterization needed?
No digital chip is possible without cell models. These cell models are produced by cell characterization using commercial softwares like guna.

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HDL Design House Opens New Office in Thessaloniki, Greece

October 04, 2016, anysilicon


Belgrade, Serbia – October 4th, 2016 – HDL Design House, provider of high performance digital and analog IP cores and SoC design and verification services, is pleased to announce the official opening of its new development center in Thessaloniki, Greece, to better serve and more efficiently handle the growing number

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Is Charge Sharing Silently Killing your ASIC Design?

October 01, 2016, anysilicon


Sharing is caring, unless it is as vital as required charge to function your ASIC design. As we move down from 20nm and below on designs with low voltages, charge sharing is quickly becoming mission critical problem in high performance custom ASIC designs using dynamic logic. Moderate charge sharing may slow down your circuits,

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