Category Archives: ASIC Design

eInfochips Positioned in the Leadership Zone for Semiconductor Services

January 17, 2017, anysilicon

eInfochips, a leading Product Engineering and Software R&D services firm, recently announced that the company was rated in the “Leadership Zone” for Semiconductor services by Zinnov, in its annual “Zinnov Zones 2016 PES” ratings. eInfochips was also recognized under “Execution Zone” for Aerospace, Industrial Automation, Medical Devices, and Consumer Software. Read More

AnSem expands operations in Enschede, The Netherlands

December 22, 2016, anysilicon

Leuven, December 20th 2016 – AnSem NV, the leading analog, RF and mixed-signal ASIC solutions company expands its operations, opening an office in Enschede, The Netherlands.
 
The Dutch design center will be headed by Clemens Mensink, who has over 20 years of IC experience. AnSem BV will be located

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HDL Design House Selected as ARM Approved Design Partner

December 20, 2016, anysilicon

Belgrade, Serbia – December 20th, 2016 – HDL Design House, a provider of high-performance digital and analog IP cores and system-on-chip (SoC) design and verification services, has joined the ARM® Approved Design Partner program, through which leading SoC design houses are recognized by ARM as accredited partners in specific technologies

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Dual Port RAM Design – The Bit Design Goals

December 12, 2016, anysilicon

It can be asked why design a dual port memory bit?  Is this not a case of re-inventing the wheel?  Not necessarily.  Most memories are designed with speed being the main design goal.  You achieve speed by limiting that range of voltages and temperatures that the memory will operate over. 

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Thermal Issues Associated with Modern ASICs – How Hot is Hot?

November 28, 2016, anysilicon

This is an interview with Moortec CTO, Oliver King about the thermal issues associated with modern ASICs and ponders the question How Hot is Hot? Oliver has been leading the development of compelling in-chip monitoring solutions to address problems associated with ever-shrinking System-on-Chip (SoC) process geometries. An analogue and mixed signal

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Join Live Webinar on the Proven Recipe for Ultra-Low-Power SoC

November 10, 2016, anysilicon

In our connected and mobile world, IC designers are striving to save µA or even nA of power consumption to extend battery usage without recharge. IoT applications bring the need for LP to new heights involving the adoption of more complex SoC architectures based on multiple power domains, which also

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