This is a guest post by Dolphin Integration which provides IP core, EDA tool and ASIC/SoC design services
To reduce the Bill-of-Material (BoM) and to simplify their usage, System-on-Chips (SoC) become more and more complex due to the integration of a large number of features previously located on board. This increase
This is a guest post by PLDA which designs and sells intellectual property (IP) cores and prototyping tools for ASIC and FPGA
You are on a very strict schedule for your next chip. Not wanting to reinvent the wheel, you plan to go to an outside vendor for some of your
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This is a guest post by Naman Gupta, a Static Timing Analysis (STA) engineer at a leading semiconductor company in India.
In accordance with the Moore’s Law, the number of transistors on integrated circuits doubles after every two years. While such high packing densities allow more functionality to be incorporated on
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It’s no secret that Google, Amazon and Apple are heavily involved in the semiconductor industry. Apple itself is the biggest buyer of chips and estimated to buy 10% of chips sold worldwide. Google uses Intel’s CPUs in their server farms and represent alone 4% of Intel total sales.
Both
This is a guest post by Naman Gupta, a Static Timing Analysis (STA) engineer at a leading semiconductor company in India.
Electrostatic Discharge and Electromigration might sound similar, but refer to two different physical phenomena. Let’s take them up one by one.
Electrostatic Discharge (ESD) is the large current flow between any
This is a guest post by Naman Gupta, a Static Timing Analysis (STA) engineer at a leading semiconductor company in India.
Lock-Up Latches are important elements for STA engineer while closing timing on their DFT Modes: particularly the hold timing closure of the Shift Mode. While shifting, the scan chains