Chip production testing is probably the most underestimated task by ASIC development engineers. And yet, testing is an essential step with a direct impact on final chip cost.
Let’s start with the basics. Testing of chips is necessary because the chip manufacturing process cannot provide 100% yield. Silicon foundries
Calculating the number of Dies Per Wafer (DPW) is a very simple and straight forward task. It’s actually based on basic high school mathematics which are related to circle area formula, remember Pi?
Silicon dies which are placed on a wafer can also be described as many
Early on in Chip projects, yield is not taken very seriously. The common thinking goes – anyhow there isn’t much to do as this early point of time. However, there are actually several things you can do even before the Chip design starts, which will translate to clear savings.
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QFN package is probably the most successful package type today. Offering low price, excellent performance and small size, it is an ideal package for many applications.
QFN (quad-flat no-leads) is a plastic SMT package consisting of: a leadframe, single or multiple dies, wirebonds and a molding compound. The
There are many ways to deliver, package and transport silicon products. Here’s a short primer that provides the basic facts regarding how silicon can be packed and delivered to ensure safe transportation with minimum damages.
There are two main options for receiving wafers from your foundry: tested or untested.
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Do you know someone that is not eager to reduce their ASIC production costs? I don’t. Some say that redesign changes can lead to significant cost reduction, for instance – using a more advanced silicon technology node to shrink the die size. True, but this is a really big, painful
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