AnySilicon IP Vendor Spotlight: Avionics communication interfaces demand precise timing, dependable data handling and extensive verification. For FPGA design teams, developing these protocol functions from scratch can add significant integration and validation effort.
In this spotlight, Ates Berna, General Manager and Managing Partner of ElectraIC, introduces the company’s avionics IP core family covering MIL-STD-1553B, ARINC 429 and ARINC 664 Part 7. We examine the design problems these cores address, their technical features, and the licensing and verification material available to customers.
About ElectraIC
ElectraIC is an electronic design and verification company founded in 2014, with offices in Türkiye, Belgium and the Netherlands. The company provides digital IC design, embedded software, electronic board and equipment design, advanced verification and functional-safety engineering. ElectraIC also develops high-reliability IP cores and embedded-system products for defense, aerospace and other safety-critical applications. Its portfolio includes communication, interface, cryptographic and processing IP for ASIC and FPGA platforms, supported by customization, integration and verification expertise.
What makes avionics communication IP challenging to integrate?
Each protocol brings a different engineering challenge. A MIL-STD-1553B implementation must coordinate bus control, terminal operation, monitoring, host communication and error handling. ARINC 429 designs need scalable receive/transmit channels with filtering and buffering. ARINC 664 Part 7 adds deterministic Ethernet communication, Virtual Link scheduling and redundant network paths.
ElectraIC’s approach is to provide configurable FPGA IP cores with defined host interfaces and supporting engineering documentation, reducing the amount of protocol-specific functionality a customer needs to develop internally.
MIL-STD-1553B IP Core: Multiple bus functions in one FPGA implementation
ElectraIC’s MIL-STD-1553 IP Core implements communication between a host processor and an external MIL-STD-1553 transceiver. A key feature is its ability to operate as a Bus Controller, two independent Remote Terminals and a Bus Monitor simultaneously.
The core supports AXI4-Lite or an asynchronous host interface and is offered as synthesizable VHDL RTL or as a targeted FPGA netlist. It is also available through the AMD Vivado IP Catalog. Customers can select narrower licensing configurations such as a single Remote Terminal, Bus Controller or Bus Monitor, depending on system requirements.
For integration, ElectraIC supplies documentation, synthesis scripts, a testbench and reference designs for Xilinx devices. Optional packages include a SystemVerilog/UVM verification environment and DO-254 certification data, subject to the applicable licensing terms.
ARINC 429 IP Core: Scalable multichannel receive and transmit processing
The ARINC429 IP Core combines receiver and transmitter processing, controller logic, internal memory, filtering, buffering and external-memory access.
Its configurable architecture supports up to 32 receive channels and 16 transmit channels, operating at the two standard ARINC 429 rates of 12.5 kbit/s and 100 kbit/s. It also provides 1,024-word individual and circular buffers per channel, SDI/ESSM/Label filtering implemented in the FPGA, and a 32-bit AXI interface for host and memory communication.
