Hello POP3,
Corner/Spilt lot is usually used for the following:
1. Device characterization (both on ATE and System).
2. Device reliability qualification (mainly in HTOL).
3. Test program robustness.
It is a good practice to produce a split lot for any new product or product families.
Usually this is 12 wafer lot, where every 2 wafers are processed to a different corner (Slow/Fast/Typical for both Core and IO).
You can also ask to vary additional parameters if you know that your design is sensitive to them (e.g.: specific capacitance).