The IP Blame Game

This is a guest post by Methodics that delivers state-of-the-art semiconductor data management (DM)  for analog, digital and SoC  design  teams.

The topic of IP quality in the SoC era is difficult to define, and solutions to problems relating to IP quality, verification, and use are hard to find. Debates rage between IP users, suppliers, and EDA vendors about where the responsibility lies for making quality IP available for use and re-use in an efficient, predictable, and scalable manner.


The use of IP—whether internally developed or sourced from a third party—is inherently complex. IC and SoC projects require a large volume of IP blocks, and the difficulty of managing this volume is compounded by factors such as geographically diverse design teams, a lack of standards for IP use and quality, and shifting design parameters. Today, many design organizations struggle to keep project data organized properly and to communicate changes effectively. Finally, exacerbating the situation, companies suffer from poor or no permission management strategy, bad performance, inconsistent data management systems, and spiraling disk/network resource requirements.



While there are many tools available to help verify, debug, assemble and otherwise manipulate IP, there’s a distinct absence of solid design data management systems that address the specific needs of IC and SoC designers. As a result, IP use often suffers from a bad rap, at least when quality is at issue. Users blame providers, and tool vendors and CAD managers are often caught in the middle, trying to put together solutions that track changes, understand and monitor IP use and quality with models, and offer some degree of version control. Complicating matters is the fact that the term “IP quality” has different meanings to different people: Is IP quality 1) the functional correctness of the IP—does it work they way it is supposed to (i.e., is it bug free)? or 2) defined by the IP’s ability to do what is expected with respect to design parameters such as power, timing, area, etc.?


Developing and integrating quality IP by either or both of those definitions requires a system that can effectively track changes and input across the entire design team at the desktop level and provide real-time access to a wide range of meta data and quality information on IP, as well as keep project managers and other senior management informed on how the use of IP is impacting schedules, budgets and design resources.


Historically, there has been no single way to control, measure, or manage the use of IP in IC and SoC projects. In the past, designers used relatively simplistic RCS/CVS file versioning to manage changes in designs. Over the years, next generation DM (data management) tools emerged that improved performance and reliability. These tools added a layer of abstraction over the file versioning problem. As designs became more complex and design teams diversified, it became common to have multiple DM repositories and even multiple DM tools used on a single project. Companies have also addressed IP management problems through proprietary solutions, or have tried to integrate enterprise PLM (Project Life-Cycle Management) systems.


These approaches have not solved the problems efficiently and effectively, but rather are time-consuming and distracting for an organization that needs to be focused on IC and SoC design rather than project management systems. Further, none provides a complete way to address the specific needs of a complex SOC project.


An SoC-oriented design data management system as shown on the right can dramatically improve IP quality. Improvements in the way designers can access IP information ‘on-the-fly’ and use it to ensure they are utilizing functionally-correct and design-appropriate IP will pay huge dividends. Of course, such a system must be easily integrated within the existing design flow and be non-disruptive to designers. If implemented correctly, a robust DM solution not only ensures higher levels of IP quality, but will result in significant improvements in designer productivity, development costs, and time to market. And, maybe even end the finger pointing!

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