Engineer II – Verification

Microchip Technology Inc. is seeking an Engineer II – Verification to join its dsPIC Business Unit in Chandler, Arizona. This role offers a unique opportunity to be part of a global team dedicated to designing technology that powers the world, within a culture that emphasizes trust, empowerment, and diversity. The company is committed to employee development and offers numerous career growth opportunities through its recognized Leadership Passage Programs.

Responsibilities:

• Develop and maintain UVM/SystemVerilog-based verification environments and Formal Tool based verification environments.
• Define test plans, implement constrained-random and directed tests, develop assertions, coverage, and drive coverage closure.
• Debug RTL and testbench issues, perform root cause analysis, and collaborate with design and architecture teams to resolve bugs.
• Analyze code and functional coverage metrics to ensure comprehensive verification closure.
• Work with the product development team to integrate the UVM test bench and tests at the SoC level.
• Collaborate with Architect, Design, and applications groups to verify the products and IP requirements.
• Continuously improve verification methodology, reuse, and efficiency.

Qualifications:

• Bachelor’s or Master’s degree in Electrical/Electronics/Computer Engineering or related field.
• Minimum 1-2 years of experience in ASIC/SoC functional verification.
• Hands-on experience in SystemVerilog language, assertions, and UVM methodology.
• Experience in developing IP level and SoC-level verification environments with UVM methodology.
• Good understanding of Digital Design, RTL fundamentals, and simulation/debug flows.

Skills:

• Strong analytical and debugging skills.
• Excellent communication, teamwork, and problem-solving abilities.
• Highly motivated, detail-oriented, and committed to delivering quality results.