Jobs Archive

CPU Core Physical Design Engineer

Intel
Folsom, CA•Hybrid work

Overview: Join Intel's Full Chip Timing (FCT) Design Automation team, where we focus on enabling seamless timing closure and optimization across the backend flow of CPU designs. We are dedicated to creating world-changing technology that enriches lives globally. If you are passionate about engineering and innovation, this is your opportunity to contribute to building a better tomorrow.

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Associate Engineer, Physical Design Engineering

Analog Devices
San Jose, CA 95134

Overview: Analog Devices, Inc. (ADI) is a global semiconductor leader focused on bridging the physical and digital worlds to drive advancements in various sectors, including AI, data centers, and digital healthcare. The company is seeking a New College Graduate Physical Design Engineer to join its Silicon Engineering team, contributing to next-generation IP designs and collaborating with various teams to deliver high-quality silicon solutions.

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ASIC RTL Design Engineer, ML Accelerators, University Graduate

Google
Sunnyvale, CA

Overview: Join Google's AI and Infrastructure team as an ASIC Design Engineer, where you'll contribute to the development of cutting-edge TPU technology that powers AI/ML applications. This role involves designing and verifying complex digital designs, focusing on custom silicon solutions for data center accelerators.

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ASIC Design Engineer, Senior

Tokyo Electron Limited
2400 GROVE BLVD, Austin, TX 78741

Overview: Join TEL as a key contributor in the design and implementation of custom VLSI test chips. This role involves developing automation scripts, performing verification simulations, and collaborating with engineering teams to ensure seamless integration of ASIC designs.

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ASIC Design Verification Engineer, Google Cloud

Google
Sunnyvale, CA

Overview: Join Google as an ASIC Design Verification Engineer, where you'll contribute to the development of cutting-edge TPU technology that powers AI/ML applications. This role involves shaping the future of AI/ML hardware acceleration and working on custom silicon solutions that enhance Google's data center capabilities.

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ASIC II – AMZ26051.4

Annapurna Labs (U.S.) Inc. - D63
Austin, TX

Overview: Annapurna Labs (U.S.) Inc. is seeking multiple ASIC II engineers for positions based in Austin, Texas. The role involves circuit board design, validation, and integration of hardware for server systems, focusing on high-speed PCB designs and large-scale server platform launches. Candidates will collaborate with an interdisciplinary team and may require international travel up to 10%. The position offers a salary range of $164,528 to $184,000 per year, with a standard workweek of 40 hours.

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