Senior ASIC Design Engineer

Blue Origin is seeking a Senior ASIC Design Engineer to lead the design of complex digital IP or subsystems for advanced space-based communication ASICs. This role emphasizes collaboration, safety, and innovation in developing reusable and low-cost space vehicles. The ideal candidate will have a strong technical background in RTL design and subsystem architecture, contributing to high-performance silicon for communication platforms.

Responsibilities:

• Lead the design and delivery of complex ASIC IP or subsystems from specification through RTL release.
• Define microarchitecture for high-speed, power-efficient digital signal-processing and control logic.
• Drive IP or subsystem trade studies involving throughput, latency, area, power, reliability, and schedule.
• Collaborate with systems, algorithm, and architecture teams to translate communication requirements into hardware implementations.
• Partner with verification, DFT, physical design, and firmware teams to ensure successful integration and tape-out readiness.
• Review RTL, test plans, and implementation results to maintain high design quality.
• Identify and mitigate technical risks early in the development cycle.
• Mentor junior engineers and help establish standard processes in coding, review, and debug.
• Support post-silicon bring-up and root-cause analysis of lab or field issues.

Qualifications:

• BS or MS in Electrical Engineering, Computer Engineering, or related field.
• 5–8+ years of ASIC digital design experience.
• Proven experience owning large blocks or subsystems in ASIC or FPGA development.
• Strong expertise in System Verilog/Verilog RTL design and debug.
• Working knowledge of synthesis, STA concepts, CDC/RDC, and integration flows.
• Experience balancing PPA tradeoffs in production-quality designs.
• Demonstrated ability to work across multidisciplinary teams.

Skills:

• Background in space-based communications, wireless communications, or digital modem architecture.
• Experience with channelization, beamforming, synchronization, equalization, or coding engines.
• Familiarity with radiation-tolerant or high-reliability design considerations.
• Experience with formal verification, low-power methodologies, or emulation/prototyping.
• Knowledge of high-speed interface design and data movement architectures.