Overview: Hewlett Packard Enterprise (HPE) is seeking an experienced ASIC Test Development Engineer for a hybrid role, requiring in-office work two days a week. This position focuses on developing testability solutions for ASICs, memory, and 2.5D SiPs, contributing to product development and manufacturing processes.
Read MoreOverview: The Senior Hardware Engineer is responsible for designing, developing, and validating hardware for automotive and consumer electronics, focusing on advanced measurement, sensing, and protection electronics. This role influences product strategy and ensures that hardware designs meet high standards for safety, reliability, and performance.
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{ mission: { description: At Palo Alto Networks®, our mission is to be the cybersecurity partner of choice, safeguarding our digital way of life. We envision a world where each day is safer and more secure than the last, and we are committed to innovating and disrupting the status quo in cybersecurity. }, work_environment: { description: We believe that collaboration thrives in person, which is why most of our teams work from the office full time, with flexibility when needed. This approach fosters real-time problem-solving, strengthens relationships, and enhances the precision that drives exceptional outcomes. }, job_role: { description: Join our ASIC team to contribute to the digital logic that powers our next-generation firewall platforms. You will take ownership of module design from specification through silicon bring-up, collaborating with top-tier verification and physical-design engineers to achieve ambitious performance, power, and schedule objectives. }, responsibilities: { description: [ Write clear design and micro-architecture specifications., Design SystemVerilog RTL that meets area, performance, and power targets., Verify your blocks using simulation, emulation, formal methods, and silicon bring-up., Collaborate with verification engineers to debug complex scenarios, close coverage, and implement design-for-debug features., Partner with physical-design teams to review synthesis/timing reports, rewrite RTL to close critical paths, and consult on floor-planning for congestion and routability., Innovate by piloting AI-driven design or verification flows that mitigate schedule risks. ] }, qualifications: { required: { education: BS in Electrical Engineering, Computer Engineering, or Computer Science ., experience: 10 years of front-end ASIC design ownership with a track record of shipping 2 chips to mass production., skills: [ Solid experience with PCIe core integration and lab validation., Expertise in SystemVerilog RTL., Proficiency in scripting languages such as Python, C/C++, Perl, bash, or tcsh. ], strengths: [ Defining micro-architecture from high-level requirements., Expertise in datapath design for complex synchronous/asynchronous digital logic., Debugging across simulation, emulation, and silicon., Analyzing timing, power, and area reports and driving necessary fixes., Excellent leadership, collaboration, and communication skills. ] }, preferred: { description: Knowledge in networking or cybersecurity domains, experience with DDR5 memory, Ethernet , or search-algorithm accelerators, formal-verification ownership, and hands-on silicon validation and lab bring-up are considered advantageous. } } }
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Join Microsoft’s Silicon, Cloud Hardware, and Infrastructure Engineering team as a Principal Physical Design Engineer, where you will play a crucial role in enhancing our cloud infrastructure. You will be responsible for physical design tasks at various levels, including floorplanning, synthesis, placement, and routing, while collaborating with architecture and design teams to ensure optimal performance and efficiency. Your expertise will drive the development of methodologies to improve design processes and ensure successful project milestones. The ideal candidate will possess a Doctorate or Master’s degree in Electrical or Computer Engineering, along with extensive experience in technical engineering roles. You will lead the convergence recipe development for subsystem designs and conduct physical design reviews, providing mentorship to junior engineers. Staying abreast of industry trends, you will continuously refine our physical design methodologies, contributing to the success of Microsoft’s Intelligent Cloud mission.
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Impulse, a San Francisco-based company focused on innovative home electrification solutions, is seeking an Electrical Engineer to join its hardware development team. The ideal candidate will possess a strong foundation in digital circuit design, sensor integration, and firmware development, with a hands-on approach to taking designs from concept to production. This role involves designing digital circuits and sensor interfaces for next-generation products, collaborating with cross-functional teams, and managing relationships with design and manufacturing partners. Candidates should have a BS in Electrical Engineering and at least 5 years of relevant experience, or an MS with 3 years. Proficiency in digital circuit design, firmware development in C/C++, and experience with test automation scripts is essential. The position offers meaningful equity, generous benefits, and the chance to work on cutting-edge technology. Impulse is committed to diversity and inclusion, ensuring a welcoming environment for all employees.
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Join the Microsoft Silicon, Cloud Hardware, and Infrastructure Engineering team, where you will play a pivotal role in advancing Microsoft’s Intelligent Cloud mission. As a DPU Silicon Engineer, you will leverage your expertise in pre-silicon verification, performance modeling, and post-silicon validation to enhance our cutting-edge Data Processing Unit technology. Your responsibilities will include defining verification strategies, developing performance models, and driving comprehensive validation strategies to ensure the highest quality and performance of our silicon products. To succeed in this role, you should possess a doctorate or relevant degree in Electrical Engineering, Computer Engineering, or Computer Science, along with significant technical engineering experience. Preferred qualifications include experience with large verification projects, proficiency in UVM/SystemVerilog, and familiarity with AI-based tools. If you are passionate about innovation and eager to contribute to a dynamic team, we invite you to apply and help shape the future of cloud infrastructure at Microsoft.
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