Senior Design Verification Architect

MediaTek is seeking a Senior Design Verification Architect to lead the verification strategy and architecture for High-Performance Computing (HPC) System on Chips (SoCs), subsystems, and IP blocks. This role involves defining comprehensive verification plans, guiding teams towards methodology and coverage goals, and ensuring high-quality silicon through a robust verification infrastructure.

Responsibilities:

• Define and document the global verification strategy, testbench architecture, and methodologies.
• Drive the adoption of industry-standard methodologies and best practices to maximize verification efficiency and reuse.
• Develop strategies to verify complex dataflow architectures using real-world AI workloads.
• Collaborate closely with RTL designers, system architects, and firmware engineers to identify edge cases and resolve complex hardware bugs.

Qualifications:

• Master's degree in Electrical Engineering, Computer Engineering, or a related field.
• Experience with Formal Verification and assertion-based verification.
• Knowledge of Emulation and FPGA prototyping (Palladium, Zebu, Protium).
• Experience with RISC-V or ARM processor-based subsystems.
• Familiarity with SystemC or C/C++ co-simulation.
• Previous experience in a technical leadership or architect role.
• Enthusiastic about AI-driven verification and familiar with using AI to optimize regression and coverage closure.

Skills:

• Verification strategy and architecture
• Methodology leadership
• AI workload verification
• Cross-functional collaboration