Physical Design Engineer II [Silicon Engineering]

SpaceX is seeking a SOC/ASIC Physical Design Engineer II to contribute to the development of next-generation ASICs for the Starlink project, which aims to provide reliable internet access globally. This role involves working with cross-disciplinary teams to enhance the performance and capabilities of the Starlink network, ultimately supporting SpaceX's mission of enabling human life on Mars.

Responsibilities:

• Perform partition synthesis and physical implementation steps including synthesis, floorplanning, and timing checks.
• Develop and improve physical design methodologies and automation scripts.
• Collaborate with the ASIC design team on architectural feasibility studies and design targets.
• Resolve design, timing, and flow issues, identifying solutions and driving execution.
• Run and debug signoff closure issues in static timing analysis and physical verification.

Qualifications:

• Bachelor's degree in electrical engineering, computer engineering, or computer science.
• 3+ years of professional experience in RTL2GDSII physical design or physical design flow development.

Skills:

• Experience with industry-standard EDA tools and their underlying algorithms.
• Knowledge of deep sub-micron FinFET and CMOS solid-state physics.
• Understanding of CMOS digital design principles and standard cell libraries.
• Familiarity with CMOS analog circuit and physical design.
• Good scripting skills in languages such as csh/bash, Perl, Python, TCL, and Makefile.