Senior Design Engineer – AI SoC Development

Intel’s AI SoC organization is seeking a Senior SoC Design Engineer to develop advanced products for AI applications. This role involves defining, implementing, and validating complex SoC IP blocks while collaborating with various teams to ensure high-quality silicon delivery.

Responsibilities:

• Evaluate trade-offs across features, performance targets, power constraints, and system limitations.
• Define and document microarchitecture for complex SoC IP blocks; implement RTL in Verilog/SystemVerilog and deliver synthesis- and timing-clean designs.
• Collaborate with verification teams to ensure comprehensive coverage and robust validation of design aspects.
• Develop and maintain timing constraints; guide physical design teams on synthesis, timing closure, and formal equivalence checks.
• Drive post-silicon validation, debug, and performance analysis.
• Mentor junior engineers and contribute to best practices for design methodology and quality.
• Perform quality checks across RTL, timing, and power convergence.
• Apply secure development practices to address security threat models and objectives.
• Collaborate with IP providers for integration and validation at the SoC level.
• Drive compliance for smooth IP-to-SoC handoff.

Qualifications:

• Bachelor's or master's degree in electrical engineering, Computer Engineering, or Computer Science or related field with 10+ years of experience.
• 7+ years of experience in RTL design and implementation for ASIC/SoC development.

Skills:

• Ability to lead projects and work cross-functionally under tight schedules.
• Strong communication skills and a collaborative mindset.
• Proven ability to solve complex design challenges such as clock domain crossings, power optimization, and timing closure.
• Hands-on experience with SoC system integration and multicore CPU subsystem design.
• Strong knowledge of standard bus protocols (AXI, AHB, etc.) and embedded processor architectures.
• Expertise in high-speed and low-power design techniques.
• Proficiency in scripting (Python, TCL, etc.) for automation and design flow optimization.
• Familiarity with industry-standard EDA tools: HDL simulators (VCS, Questa, IES), lint tools (Spyglass), and FPGA prototyping tools (Xilinx Vivado, Altera Quartus II).