Senior Staff Engineer, ASIC/VLSI Synthesis and Design

Marvell is a leading provider of semiconductor solutions that form the backbone of data infrastructure across various sectors, including enterprise, cloud, AI, and carrier architectures. The company is focused on innovative technology that drives meaningful change and enhances the efficiency of data processing, particularly in the realm of Generative AI and accelerated computing. Marvell's Photonic Fabric™ technology represents a significant advancement in interconnect solutions, offering high bandwidth and low latency for AI accelerators and GPUs, thereby optimizing performance and reducing costs for hyperscalers.

Responsibilities:

• Develop and validate timing constraints for intricate SoC designs.
• Collaborate with Architecture, RTL, DFT, and Analog teams to analyze timing complexities and develop consolidated timing modes and constraints.
• Own and contribute to Front-End Implementation tasks such as Synthesis, UPF development, Logical Equivalence Checks (LEC), and Functional ECOs.
• Analyze trade-offs between power, performance, and area goals to drive chip implementation flows.
• Perform Physical Aware Synthesis using industry-standard tools like Fusion Compiler.
• Resolve tool issues independently or with EDA tool vendors.
• Automate Front End Flows and processes using scripting languages like Tcl or Python.
• Ensure compliance with Netlist Handoff checklists for delivery to PD.
• Document best practices and lessons learned for continuous improvement.

Qualifications:

• Bachelor’s degree in Computer Science, Electrical Engineering, or related fields with 5-10 years of experience, or a Master’s/PhD with 3-5 years of experience.
• Minimum of 5 years of industry experience in ASIC implementation and synthesis.
• Strong understanding of ASIC design flows from RTL to GDSII.
• Knowledge and hands-on experience with synthesis and STA methodologies.
• Proficiency in using synthesis tools, STA tools, and scripting languages (e.g., Tcl, Perl).
• Experience with high-complexity silicon in advanced technology nodes, preferably TSMC N4/N5.
• Strong understanding of timing constraint development for hierarchical designs.
• Experience with functional ECOs using industry-standard tools and flows like Conformal ECO.
• Familiarity with UPF development for blocks and SoCs.

Skills:

• Expertise in timing constraints development and synthesis methodologies.
• Proficient in scripting languages such as Tcl and Python.
• Strong analytical skills for timing analysis and optimization.
• Ability to collaborate effectively with cross-functional teams.
• Experience with Physical Aware Synthesis and EDA tools.