Sr. Principal Engineer, IP Design [ASIC]

SK Hynix Memory Solution is a global leader in semiconductor innovation, specializing in advanced memory solutions for devices ranging from smartphones to data centers. The company is committed to sustainability and is at the forefront of technological advancements, including AI and machine learning. We are seeking innovative individuals to join our team and contribute to the development of next-generation memory solutions.

Responsibilities:

• Lead end-to-end IP ownership for high-performance memory controllers, from specification to tapeout.
• Develop efficient, high-speed RTL (Verilog/SystemVerilog) for critical modules, optimizing for power, performance, and area (PPA).
• Oversee design reviews, linting, CDC analysis, and power analysis to ensure robust functional and timing closure.
• Collaborate with verification, DFT, physical design, and firmware teams to resolve system-level bottlenecks and ensure seamless integration.
• Drive enhancements in design automation and best practices for synthesis and static timing analysis (STA).
• Mentor junior and staff engineers on advanced design techniques, code quality, and debugging strategies.

Qualifications:

• Bachelor's degree in Electrical Engineering, Computer Engineering, or related field.
• 12+ years of hands-on experience in ASIC/SoC design with a proven track record of successful tapeouts.
• Expert proficiency in Verilog/SystemVerilog, logic design, synthesis, and STA for high-speed digital circuits.
• Strong experience with industry-standard EDA tools (Synopsys/Cadence) for simulation, linting, and CDC analysis.
• Demonstrated ability to lead technical discussions and document complex micro-architectures clearly.

Skills:

• Advanced education (Master's or PhD) in Electrical Engineering with 8+ years of applicable experience.
• Deep understanding of memory controller architectures (PCIe/NVMe, DDR, NAND Flash) or error correction algorithms.
• Experience designing for high-frequency interfaces or data center/enterprise applications.
• Proficiency in Python, Tcl, or Perl for design automation and flow optimization.
• Previous experience serving as a technical lead or architect for a major subsystem or IP block.