Sr./Staff/Sr. Staff ASIC Design Engineer

We are looking for a skilled ASIC Design Engineer to join our team, responsible for RTL design through to tapeout readiness. The role offers opportunities for mentorship and design methodology improvements, with responsibilities increasing based on seniority (Sr., Staff, Sr. Staff).

Responsibilities:

• Design, simulate, and verify RTL modules using Verilog/SystemVerilog.
• Participate in design reviews, linting, CDC, and power analysis.
• Debug and resolve functional/timing issues across design stages.
• Collaborate with verification, DFT, physical design, and architecture teams.
• Contribute to design automation (Tcl/Python/Perl scripts) and methodology enhancements.
• Own complex IP blocks or subsystems end-to-end (from spec to tapeout) for Staff/Sr. Staff levels.
• Lead design reviews, drive design signoff, and ensure quality across the team for Staff/Sr. Staff levels.
• Mentor junior engineers and set best practices for RTL coding, linting, CDC, etc. for Staff/Sr. Staff levels.
• Interface with cross-functional teams to resolve critical issues for Staff/Sr. Staff levels.
• Contribute to architecture discussions and micro-architecture trade-offs for Staff/Sr. Staff levels.

Qualifications:

• 3+ years of industrial experience in ASIC design.
• Strong proficiency in RTL design using Verilog/SystemVerilog; familiarity with UVM is a plus.
• Familiarity with standard interfaces (AXI, AHB, APB, SMBus, UART, etc.).
• Proficiency in Tcl/Python/Perl/Shell for automation and flow customization.
• Strong communication, problem-solving, and teamwork skills.

Skills:

• Successful tapeout(s) in advanced nodes (preferred).
• Experience with ARM/RISC-V-based SoCs or custom accelerators (preferred).
• Experience with UVM-based testbenches (preferred).
• Knowledge of UPF/CPF, power gating, clock gating (preferred).
• Understanding of floorplanning, placement, routing impact on timing (preferred).
• Demonstrated ability to lead design efforts or mentor (for Staff/Sr. Staff roles).