Semiconductor Latest News

MOSCHIP Announces High Speed Serial Trace Probe (HSSTP) PHY With Link Layer in 6nm

Santa Clara, CA, – April 18, 2022 – MosChip Technologies, a semiconductor and system design services company, unveils today  enhanced simplex High Speed Serial Trace Probe (HSSTP) PHY macro with link layer supporting  data transfer capabilities of up-to 12.5Gbps per lane in 6nm FinFET technology. MosChip has over a twenty-year track

Faraday Launches Cortex-A53-based Platform to Accelerate FinFET SoC Development

Faraday Technology Corporation (TWSE: 3035), leading ASIC design service and IP provider, today launched SoCreative!VI™ A600 SoC development platform implemented in Samsung Foundry’s 14LPP FinFET process technology. This platform is equipped with Faraday’s A600 SoC chip on an evaluation board and the Linux software development kit (SDK) to create a full-performance system

ATS Engineering and ChipTest Announce Strategic Collaboration for Test Program Development for Advantest’s customers

Tel Aviv, Israel – March 24, 2022 – ATS Engineering, a leading Israeli test house, and ChipTest Semiconductor IC Test Company, have announced an exclusive collaboration agreement for developing test programs and test interfaces (load boards and probe cards) on the ATS’ Advantest V93000 Smart Scale platform, to support ATS

Introduction to System in Package (SiP)

System in Package (SiP) is a method used for bundling multiple integrated circuits (ICs) and passive components into a single package, under which they all work together. This contrasts to a System on Chip (SoC), whereas the functions on those chips are integrated into the same die.
 

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Understanding Wafer Level Packaging

Wafer Level Packaging or WLP,  is a type of IC packaging technology that is performed at wafer level. This means that the packaging is applied on whole wafers and wafers are diced only after the packaging is successfully competed. In wafer level packaging, the components used in assembly (such as

Silex Insight launches DDR encrypter for High-Performing Systems (ASIC/FPGA)

Silex Insight, a leading provider of cryptographic IP solutions, is now extending their offering by launching a high throughput DDR encrypter (100Gbps). The DDR encrypter IP Core module enables on-the-fly encryption and authentication to the external memory. It is highly configurable and may be optimized for various size, throughput, and

Semicondcutor Foundry Sales Forecast 2016-2022

IC Insights’ forecast for the foundry market through 2026 was part of its recently released 1Q Update to the 2022 McClean Report.  The Update also included analyses of the top-25 2021 semiconductor suppliers, semiconductor industry capital spending, IC industry capacity, the automotive IC market, and detailed forecasts for the DRAM, flash, MCU, MPU, and analog

Semi Industry Capex Forecast to Jump 24% and Reach Over $190 Billion This Year

Figure 1 shows that after surging 36% in 2021, semiconductor industry capital spending is forecast to jump 24% in 2022 to a new all-time high of $190.4 billion, up 86% from just three years earlier in 2019. Moreover, if capital spending increases by ≥10% in 2022, it would mark the

Silicon Wafer Cost

Wafer cost is a critical component of IC cost calculation. Wafer cost is based on 4 main factors: wafer technology node, e.g. 5nm, 65nm, 130nm, etc. Wafer options/features, e.g. all the options required on top of the plain vanilla, e.g. mim cap, flash, high voltage, etc. Wafer volume, e.g. how

Introduction to Physical Design

There are numerous steps that are involved in the design of digital (or mixed signal) circuits starting from system specifications right till the chip is manufactured. One of these steps is a process of transforming a functionally described circuit (normally in netlist) into physical layout at the lowest level (normally