What Is Latch Up and How to Test It

October 01, 2013, anysilicon

Simply defined, Latch-Up is a functional chip failure associated with excessive current going through the chip, caused by weak circuit design. In some cases Latch-Up can be a temporary condition that can be resolved by power cycle, but unfortunately it can also cause a fatal chip failure.


CMOS Latch-Up

The following diagram is a drawing of a typical CMOS circuit. Notice the two transistors, NPN and PNP and their connection to VDD and GND supply rails. The two transistors are protected by resistors but if examined more closely, there’s an SCR device that could possibly be triggered.


In a latch-up conduction, the current flows from VDD to GND directly via the two transistors, causing the dangerous condition of a short circuit. The resistors are bypassed and thus excessive current flows from VDD to Ground.

Latch-up Test

There are many vendors that provide latch up testing services. The test is a series of attempts that trigger the SCR structure within the CMOS IC while the relevant pins are monitored for overcurrent behaviour.

It’s recommended to take the very first samples from the engineering lot or MPW run and send them to a Latch-up testing lab. The lab will apply the maximum possible supply power and then inject current to the chip inputs and outputs while measuring if a Latch-up occurs by monitoring the supply current.

Do you need Latch-up testing services? We’d be glad to help you, just click here.

  • http://Morespecifically, Tom

    Latch-up is the result of exciting a parasitic structure similar to a discrete SCR. It is activated by forcing current through an I/O. Once activated it causes a low impedance path to ground from the power source resulting in high currents, which in turn result in current starvation elsewhere, voltage droop, over-heating etc. As with a SCR, it is turned off by removing the trigger current and power source. The trigger current alone will not deactivate the device.

    This is something best handled by proper design and verified through characterization. Test it the same way you would characterize an SCR.

  • Jerome Barry

    A parasitic NPN exists in CMOS devices with Nwell as collector, Psub as emitter, and Nwell as base.

    When this parasitic device turns on, current flows efficiently from the high voltage on the Nwell to the low voltage of the substrate. This lets the smoke out of the package.
    Robust design merely requires that sufficient resistance exist between the collector and the base, and this is accomplished with spatial separation. LU risks are highest near MOS devices connected directly to an external pad. For this reason, spacing and guard rings are used to both achieve spatial separation and prevent the parasitic device turning on.

  • http://LATCH-UP VENKAT

    Yes, Latch up is the phenomena where there exists a short circuit path between the supply and ground due to the parasitic, which increases the current for each loop, there by the device gets heated up and at some point of time breaks down. I think Physical design guys will take care of this by providing Well Taps and Gaurd rings to prevent the transistor from latching.

    Please let me know how DFT can handle this..??


  • superzoom

    Are there any specific ANSI standards for CMOS latchup immunity?