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Hardware Design Engineer

Published Date: February 19, 2026
SambaNova Systems, San Jose, CA•Remote
Job Description:

SambaNova Systems is seeking Hardware Design Engineers to contribute to the development of the SambaNova Suite™, a pioneering generative AI platform. This role involves designing components for Reconfigurable Dataflow Unit ASICs, collaborating with various engineering teams to enhance hardware features that deliver unique value to the organization.

Responsibilities:

  • Define and document microarchitecture specifications for complex digital design elements.
  • Code, integrate, and debug SystemVerilog RTL designs throughout the chip implementation and production lifecycle.
  • Achieve targets for Power, Performance, and Area (PPA) using advanced digital design techniques.
  • Collaborate with design verification and physical design teams to ensure convergence.
  • Work with architects and software teams to prototype new features that enhance application-level performance.
  • Mentor junior design engineers on high-speed digital design techniques.
  • Drive improvements in the design flow using AI and automation, including new EDA tool methodologies.

Qualifications:

  • Master's or PhD degree in Computer Engineering or Electrical Engineering.
  • Strong background in computer architecture and digital logic design.
  • Knowledge of AI workload acceleration techniques and industry-standard interconnects and protocols (e.g., AXI, PCIe, Ethernet, HBM/DDR).
  • Mastery of SystemVerilog design techniques for high-speed, high-performance ASICs.
  • Experience in digital logic synthesis tools and Static Timing Analysis (STA).
  • Proficiency in industry-standard tools for linting, Clock Domain Crossing (CDC), and Logical Equivalence Checking (LEC).
  • Experience implementing SystemVerilog Assertions (SVA) for design intent verification.
  • Familiarity with Git version control for managing release cycles.
  • Scripting skills in Python and Linux Shell.

Skills:

  • Advanced digital design techniques
  • SystemVerilog RTL coding
  • Power, Performance, and Area (PPA) optimization
  • Collaboration with cross-functional teams
  • Mentoring and leadership
  • AI and automation in design flow
  • Proficiency in digital logic synthesis and timing analysis tools

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