ASIC Design Verification Lead

Eridu AI is a Silicon Valley-based hardware startup focused on innovative infrastructure solutions that enhance the training and inference capabilities of large-scale AI models. The company addresses system-level bottlenecks in AI performance through groundbreaking advancements in semiconductors, software, and systems, validated by leading hyperscalers. Led by experienced executives and engineers, Eridu AI is at the forefront of AI technology development.

Responsibilities:

• Define and own verification strategies at block, subsystem, and chip levels.
• Develop scalable verification environments using SystemVerilog and UVM.
• Drive execution from test-plan definition through coverage and bug closure.
• Ensure verification readiness for tape-out as a gating requirement.
• Write and review high-quality testbenches, sequences, checkers, and scoreboards.
• Develop various tests to validate complex corner cases.
• Debug functional failures across RTL, testbench, and simulation environments.
• Define coverage goals and analyze results to identify gaps.
• Provide actionable feedback to RTL designers for quality improvement.
• Collaborate with RTL, architecture, physical design, and firmware teams.
• Conduct root-cause analysis of functional and integration issues.
• Support gate-level, timing-aware, and power-aware simulations.
• Lead full-chip verification planning and execution.
• Ensure clean handoff to silicon bring-up teams with confidence in design correctness.
• Establish verification checklists and quality gates.
• Track verification progress and proactively escalate issues.
• Continuously improve verification methodologies and best practices.

Qualifications:

• Strong hands-on experience in ASIC design verification.
• Proven track record of taking at least one complex ASIC to tape-out with direct verification ownership.
• Deep expertise in SystemVerilog and UVM-based verification methodologies.
• Strong understanding of ASIC design and verification flows, including simulation and debug.
• Experience with block-level through full-chip verification and integration.
• Ability to drive execution in fast-paced startup environments.
• Excellent communication skills for cross-disciplinary collaboration.

Skills:

• Networking ASIC verification experience (preferably Ethernet-based systems).
• Experience with gate-level, timing-aware, and low-power verification.
• Familiarity with high-speed interfaces and chip-to-chip interconnects.
• Experience with emulation, acceleration, or FPGA-based validation.
• Post-silicon debug experience and RTL-to-silicon correlation.