Lead Digital ASIC Design Engineer

K2 is a pioneering space startup focused on developing the largest and most powerful satellites ever built, aiming to revolutionize satellite technology for various orbits. With significant funding and contracts, K2 is positioned to lead in the mass production of high-performance satellite platforms, contributing to the advancement of space exploration and technology.

Responsibilities:

• Lead and manage a team of digital design engineers, providing mentorship and performance management.
• Manage development schedules, track deliverables, and report status to senior leadership.
• Contribute to the design and implementation of microarchitecture and RTL for key digital blocks in wireless SoCs.
• Collaborate with system architects to translate high-level DSP algorithms into efficient hardware implementations.
• Develop RTL for complex digital subsystems such as filters, beamformers, and digital front-ends.
• Contribute to the design and integration of digital blocks for various system interfaces.
• Optimize designs for power, performance, and area while meeting constraints.
• Collaborate with synthesis and backend teams to achieve timing closure and resolve design issues.
• Contribute to verification planning and validate complex digital subsystems with verification teams.
• Participate in chip bring-up and lab validation activities for digital subsystems.
• Support products through production and spaceflight operations.
• Mentor junior engineers and contribute to team technical growth.

Qualifications:

• B.S. or M.S. in Electrical Engineering, Computer Engineering, or related field.
• 10+ years of industry experience in digital ASIC design with ownership of complex digital blocks.
• 3+ years of experience leading ASIC design teams or projects.
• Strong proficiency in RTL design using SystemVerilog or Verilog.
• Experience in microarchitecture definition and implementation based on architectural guidelines.
• Hands-on experience with timing closure and static timing analysis.
• Familiarity with DFT concepts and tools for scan and BIST insertion.
• Solid understanding of SoC design flows and verification methodologies.
• Experience with DSP blocks for wireless communication systems.
• Proficiency with industry-standard EDA tools for design and analysis.

Skills:

• Strong debugging and problem-solving skills.
• Excellent communication skills for cross-functional collaboration.
• Proficiency in RTL design and synthesis tools.
• Experience with timing closure and static timing analysis.
• Knowledge of DSP algorithms for wireless systems.